MPEG-2 decoding with a reduced RAM requisite by ADPCM recompression before storing MPEG decompressed data

Claim 2

The method according to claim 1, characterized in that it comprises preventively subdividing each block of n∗m pels into two sub-blocks of (n/2)∗m pels and carrying out said ADPCM recompression, coding-decoding and ADPCM decompression on said sub-blocks.

Claim 3

MPEG-2 video decoder, interfacing with a control bus and a data bus through which video data are written and read in respective RAM buffers extemal to the "core" of the video decoder which comprises a first "first-in-first-out" (FIFO) buffer for data acquisition and writing in a first buffer (BIT BUFFER) of an extemal DRAM memory, a start code detecting circuit (START CODE DETECTOR) synchronized by a controller (CONTROLLER), a bi-directional buffer (I/O UNIT) for on screen display data (OSD), a variable length decoder (VDL) of the compressed data input stream (BITSTREAM), an MPEG decompression block (PIPELINE-RLD, I_QUANT, I_DCT, PREDICTOR CONSTRUCTION) of the data decoded by said variable length decoder, comprising a "run length" decoder, an inverse quantizer circuit, an inverse discrete cosine transform processor, a "predictor generating circuit, a "Macroblock scan to raster scan" conversion circuit for a current B-picture upstream of a display unit, characterized in that further comprises a coding and recompression circuit (ADPCM ENCODER), according to an adaptive differential pulse code modulation scheme of the differential type, capable of recompressing decompressed I and P pictures and of coding the respective data to be stored in the respective buffers of said external memory; a decoding and decompressing and decoding circuit (ADPCM DECODER) of the stored data relative to said recompressed I and P pictures read from the respective buffers of said external memory capable of generating a stream of decoded and decompressed data relative to I and P pictures; means of motion compensation of B-pictures and of conversion "MACROBLOCK TO RASTER SCAN".

Claim 4

The decoder according to claim 3, characterized in that said recompressing and coding circuit (ADPCM ENCODER) comprises a buffer (BLOCK BUFFER) for the acquisition of blocks of decompressed I-DCT data produced by said pipeline of MPEG-2 decompression; a circuit (VARIANCE ESTIMATOR) capable of estimating the energy content of said buffer (BLOCK BUFFER) and of generating a digital value of the variance of the pel values of a block of I-DCT data to be stored in a respective buffer of said memory; programmable means for storing a plurality of pre-established digital values (ROM, PLA) selected by said digital value of variance read from said memory; a multilevel quantizer circuit (QUANTIZER) coherently conditioned by the digital value selected by the current value of the variance; a differentiating circuit (-) capable of receiving through a first input the stream of said I-DCT decompressed data block and through a second input a predictor value and to output a stream of data that are input to said multilevel quantizer circuit (QUANTIZER); a write coding circuit (CODER) of ADPCM recompressed data in the respective memory buffers, capable of receiving as input the output stream of said quantizer circuit; a generating circuit of said predictor value comprising a multiplexer (MUX) receiving through a first input the decompressed I-DCT data stream and through a second input the predictor value generated by the circuit, an adder (+) receiving through a first input the output of said quantizer circuit and through a second input the output of said multiplexer (MUX) and outputting a stream of summed data, a limiting circuit (LIM 0-255) receiving through an input said stream of summed data produced by said adder (+), followed in cascade by a circuit that generates said predictor value (COEFF) whose output is fed to a second input of said differentiating circuit (-) and of said multiplexer (MUX).

Claim 5

The decoder according to claim 4, characterized in that said programmable means (ROM, PLA) are constituted by a read only memory (ROM).

Claim 6

The decoder according to claim 4, characterized in that said programmable means of storage are constituted by a programmable logic array (PLA).

Claim 7

The decoder according to claim 4, characterized in that it comprises means (ADPCM MEMORY) for storing part of ADPCM recompressed data within the decoder.

Claim 8

The decoder according to claim 5, characterized in that said storing means (ADPCM MEMORY) are constituted by a RAM memory of 194.400 bit capacity.