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EP0778575A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Dynamic random access memory

Assignee: International Business Machines Corp
•
Filing: 1996-11-11
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Granted: —
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Expires: 2016-11-11
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Abstract

Abstract An inexpensive single-chip integrated DRAM memory system having a high density and large bandwidth is provided comprising a DRAM array 10 having a plurality of pipelined stages 12, a control logic circuit 11 for controlling said DRAM array 10, and buffer means 13 integrated onto said chip for storing data being fetched from said DRAM array. The DRAM array and said control logic and said buffer means are all integrated onto one and the same substrate 1, wherein said control logic 11 generates a control signal for controlling operations taking place in said plurality of pipelined stages and the final stage of said pipeline 12 inputs/outputs data from said buffer means 13 in a burst mode.

Inventors

  • 👤 Yasunao Katayama

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-28 09:32
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C7/00; G11C7/10; G11C7/1015; G11C7/1039

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 55 words
A dynamic random access memory (DRAM) system comprising a chip (1), a DRAM array (10) mounted on said chip having a plurality of pipelined stages (12), and control logic (11) mounted on said chip for controlling said DRAM array, said control logic including means for generating a signal for controlling said plurality of pipelined stages.
Claim 2
Dependent Claim 31 words
A DRAM system as recited in claim 1, further comprising buffer means (13) for storing data being fetched from said DRAM array, and to input/output said data in a burst mode.
Claim 3
Dependent Claim 44 words
A DRAM system as recited in claim 1 or 2, wherein said plurality of pipelined stages comprise a first stage for setting an address from which data is to be fetched and a second stage for performing internal memory operations in said DRAM array.
Claim 4
Dependent Claim 28 words
A DRAM system as recited in any preceding claim, wherein said control logic is connected to a Central Processing Unit (CPU) which is not mounted on said chip.
Claim 5
Independent Claim 118 words
A method for operating a dynamic random access memory (DRAM) system, said DRAM system having a chip (1), a DRAM array (10) mounted on said chip having a plurality of pipelined stages (12), control logic (11) mounted on said chip for controlling said DRAM array, and buffer means (13) for storing data being fetched from said DRAM array, said method including the steps of: generating a signal at the control logic for controlling said plurality of pipelined stages; and inputting/outputting said data in said buffer means in a burst mode; wherein a first period to input/output said data in a burst mode is longer than a second period for performing an internal memory operation in said DRAM array.
Claim 6
Dependent Claim 29 words
A method as recited in claim 5, wherein there are substantially no clock cycles between a first data output and a second data output, both in a burst mode.

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