Bias controller for decreasing bias current supplied to amplifier without sacrifice of distortion

Claim 2

The bias current controlling circuit as set forth in claim 1, in which said amplifier has a field effect transistor (3a), and said bias current is supplied to a gate electrode of said field effect transistor through a choke coil (3e).

Claim 3

The bias current controlling circuit as set forth in claim 1 or 2, in which said distortion detecting means includes a first detector (2c) for determining a positive peak value (VA) of said second output signal, and a second detector (2d) for determining a negative peak value (VB) of said second output signal, said positive peak value and said negative peak value being representative of said magnitude of said distortion.

Claim 4

The bias current controlling circuit as set forth in claim 3, in which a ratio between said positive peak value (VA) and said negative peak value (VB) represents said magnitude of said distortion.

Claim 5

The bias current controlling circuit as set forth in claim 3 or 4, in which said distortion detecting means further includes a directional coupler (2a) connected to said amplifier (3) so as to generate a third output signal (BR1) proportional to said second output signal (OUT2), and a coupler (2b) having a coupling condenser (2i) connected between said directional coupler (2a) and said first and second detectors (2c/2d) so as to distribute said third output signal (BR1) to said first and second detectors (2c/2D).

Claim 6

The bias current controlling circuit as set forth in claim 5, in which said first detector includes a first detecting diode (2k) having an anode connected to said coupler (2b), a first resistor (2m) connected to a cathode of said first detecting diode (2k), a first smoothing condenser (2n) connected between said first resistor (2m) and a constant potential source, and a first operational amplifier (2o) having a first non-inverted node connected to said first smoothing condenser and a first inverted node connected to an output node thereof, and said second detector (2d) includes a second detecting diode (2p) having a cathode connected to said coupler (2b), a second resistor (2q) connected to an anode of said second detecting diode (2p), a second smoothing condenser (2r) connected between said second resistor (2q) and said constant potential source, and a second operational amplifier (2s) having a second non-inverted node connected to said second smoothing condenser (2r) and a second inverted node connected to an output node thereof, a fourth output signal (OUT4) of said first operational amplifier (2o) and a fifth output signal (OUT5) of said second operational amplifier (2s) serving as said first output signal.

Claim 7

The bias current controlling circuit as set forth in any of claims 1 to 6, in which said bias current regulating means includes a mixer (2t) connected to said distortion detecting means (2a/2b/2c/2d) and producing a third output signal (IS) representative of a decrease of said bias current or an increase of said bias current from said first output signal (OUT4/OUT5), and an integrator (2u) connected to said mixer (2t) and responsive to said third output signal (IS) for varying said bias current.

Claim 8

The bias current controlling circuit as set forth in claim 1, in which said distortion detecting means includes a first detector (2c) determining a positive peak value of said second output signal (OUT2) so as to produce a third output signal (OUT4) having a first potential level representative of said positive peak value, and a second detector (2d) determining a negative peak value of said second output signal so as to produce a fourth output signal (OUT5) having a second potential level representative of said negative peak value, said third and fourth output signals serving as said first output signal, and said bias current generating means includes a mixer (2t) having a first resistor (2v) connected at one end thereof to said first detector (2c) and a second resistor (2w) connected at one end thereof to said second detector (2d) and at the other end thereof to the other end of said first resistor (2v) and operative to mix said third output signal (OUT4) with said fourth output signal (OUT5) at said other ends of said first and second resistors for generating a fifth output signal (IS) representative of a decrease of said bias current or an increase of said bias current, said first resistor (2v) and said second resistor (2w) having respective resistances adjusted to a predetermined ratio representative of said target magnitude, and an integrator (2u) connected to said mixer (2t) and responsive to said fifth output signal (IS) for regulating said bias current (BS).

Claim 9

The bias current controlling circuit as set forth in claim 8, in which said integrator (2u) includes an operational amplifier (2y) having an inverted node connected to said mixer (2t) and a non-inverted node connected to a constant potential source, and an integrating condenser (2z) connected between said inverted node and an output node of said operational amplifier.

Claim 10

The bias current controlling circuit as set forth in any of claims 1 to 9, in which said bias current controlling circuit forms a part of a transmitting section of a battery powered radio communication device.