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EP0770952A1 Expired / Lapsed EP ⏱️ 0.0 years remaining

Power management in an information processing system

Assignee: International Business Machines Corp
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Filing: 1996-09-23
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Granted: —
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Expires: 2016-09-23
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Abstract

Abstract An information processing system achieves power saving by reducing the operating frequency of a CPU, or completely halting the operation of the CPU, at appropriate times during asynchronous communication with peripheral devices. The information processing system comprises: (a) a CPU that is operated in a normal mode during which the CPU is driven at a relatively fast operating clock rate, and a power saving mode during which the operating clock has a lower rate or is halted; (b) at least one peripheral device; (c) a bus for performing communication between the CPU and the peripheral device; (d) termination detection means for detecting a completion of a predetermined transaction between the CPU and the peripheral device; (e) time counting means for measuring a predetermined period of time after the completion of the predetermined transaction; and (f) power saving control means for having the CPU enter the power saving mode until the time counted by the time counting means reaches the predetermined period of time.

Inventors

  • 👤 Shinji Matsushima
  • 👤 Seiichi Kawano
  • 👤 Masayoshi Nakano
  • 👤 Takashi Inui

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-08 15:18
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3206; G06F1/3215; Y; Y02; Y02D; Y02D10/00

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 131 words
An information processing system comprising: (a) a CPU that is operated in a normal mode during which said CPU is driven at a relatively fast operating clock rate, and a power saving mode during which said operating clock has a lower rate or is halted; (b) at least one peripheral device; (c) a bus for performing communication between said CPU and said peripheral device; (d) termination detection means for detecting a completion of a predetermined transaction between said CPU and said peripheral device; (e) time counting means for measuring a predetermined period of time after the completion of said predetermined transaction; and (f) power saving control means for having said CPU enter the power saving mode until the time counted by said time counting means reaches said predetermined period of time.
Claim 2
Dependent Claim 29 words
An information processing system as claimed in Claim 1 in which said predetermined transaction is a data transfer for one sector between said CPU and said hard disk drive.

References Cited (Backward Citations)

US5083266A Cited
EP0529269A2 Cited
EP0579369A1 Cited

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