Register and instruction controller for superscalar processor

Claim 2

The processor of claim 1 wherein each one of the plurality of execution clusters further comprises: a register file, each register file including a plurality of registers, each one of the plurality of registers having a physical address, the plurality of instructions accessing the data stored in the plurality of registers by the physical addresses, the physical addresses of the registers of the plurality of registers files being substantially disjoint among the plurality of execution clusters.

Claim 3

The processor of claim 2 wherein the plurality of instructions include instructions having operators and operands, the operands including virtual register addresses, and wherein each of the plurality of execution clusters further comprises: a register renaming unit, the register renaming unit dynamically assigning the physical addresses of the plurality of registers to the virtual register addresses according to the distribution of the plurality of instructions among the plurality of execution clusters, wherein further, the means for concurrently distributing further comprises: a distribution buffer, the distribution buffer having a plurality of locations storing the plurality of instructions while concurrently distributing to the plurality of execution clusters; and means for assigning a unique serial number to each of the plurality of instructions stored in the distribution buffer, the serial numbers assigned in the order that the plurality of instructions are fetched from a memory storing the plurality of instructions, wherein further, the distribution buffer further comprises: a plurality of pickers, there being one picker for each one of the plurality of execution clusters, each one of the plurality of pickers making a determination if a particular instruction needs to be copied from the distribution buffer to a corresponding one of the plurality of execution clusters, the particular instruction being distributed to the corresponding one of the plurality of execution clusters when each one of the plurality of pickers has made the determination, and in response to distributing the particular instruction, the means for concurrently distributing fetching a next instruction from the memory.

Claim 4

The processor of claim 3 wherein the distribution buffer further comprises: a plurality of shift registers connected to each other to determine an order in which the plurality of instructions stored in the distribution buffer are distributed to the plurality of execution clusters.

Claim 5

The processor of claim 3 wherein the distribution buffer further comprises: a ring buffer having a head pointer and a tail pointer to determine an order in which the plurality of instructions stored in the distribution buffer are distributed to the plurality of execution clusters.

Claim 6

The processor of claim 1 further comprising: means for fetching the plurality of instructions to be executed in the plurality of execution clusters dependent on a predicted execution flow of the plurality of instructions.

Claim 7

The processor of claim 1 wherein each instruction of the plurality of instructions include an operator, and wherein each of the plurality of execution clusters further comprises: a dispatch buffer, the dispatch buffer storing the plurality of instructions to be issued to the plurality of execution units of the corresponding execution cluster; and an instruction scheduling controller, connected to the dispatch buffer, issuing a particular instruction stored in the distribution buffer to a particular one of the plurality of execution units based on the operator of the particular instruction.

Claim 8

The processor of claim 3 further comprising: a central controller to manage a commitment of an executed instruction, the central controller further comprising: means for releasing temporary buffers utilized by the executed instruction if the executed instruction was successfully executed; and means for deleting all states of the executed instruction if the executed instruction was unsuccessfully executed.

Claim 9

The processor of claim 1 wherein the plurality of instructions include instructions having operators and virtual register addresses of operands, and further comprising: an instruction generator assigning the virtual register addresses to operands of the plurality of instructions in order to maximize the number of the plurality of instructions which are disjoint among the plurality of execution clusters according to the addresses of data accessed by the operands of the plurality of instructions, wherein the virtual register addresses are partitioned into a plurality of sets, there being one set for each of the plurality of execution clusters, wherein the plurality of sets further comprises: a first set having even virtual register addresses, and a second set having odd virtual register addresses.

Claim 10

The processor of claim 2 wherein the plurality of instructions include instructions having a plurality of operands, each operand having a virtual register address, and wherein a copy of a particular instruction is copied to every one of the plurality of execution clusters having physical addresses of registers corresponding to any of the virtual register addresses of the plurality of operands.