EP0758768A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
An apparatus and method of providing an extremely low-power self-awakening function to a processing unit of a communication system
Assignee: Skyworks Solutions Inc
•
Filing: 1996-07-22
•
Granted: —
•
Expires: 2016-07-22
Abstract
Abstract A low-power stop mode "snooze" timer is implemented in the processing unit of a communication system, which runs without the use of the usual crystal-controlled oscillator. The "snooze" timer is implemented by a second oscillator with associated timer circuit. The second oscillator runs continually and feeds a timer which is loaded with a suitable value. The timer, when timed out or expired, will reactivate the main processing functions, thus allowing the successful reception of an external signal from a remote transmission source. To compensate for the inaccuracy of the second oscillator due to its dependence upon voltage, process and temperature, the snooze timer's output is calibrated during the wake-up periods against a timing signal derived from the internal crystal-controlled timing source. This calibration compensates for the inherent frequency instability of the second oscillator and allows a timing signal of sufficient accuracy to be maintained over the stop cycle.
Inventors
- 👤 Mark Chapman (Nmi)
- 👤 Dennis E. Starbuck
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 21:28
CPC Classifications
H; H04; H04W; H04W52/00; H04W52/02; H04W52/0209; H04W52/0261; H04W52/0287; H04W52/029; Y; Y02; Y02D; Y02D30/00; Y02D30/70
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
23 words
A device for invoking a wakeup logic 270 of a processing unit 200, comprising: an oscillator 210; a counter 220; a detection means.
Claim 2
Independent Claim
191 words
A device for invoking a wakeup logic 270 of a processing unit 200 in an electronic system from a low-power stop mode after a predetermined time period, said electronic system comprising a first oscillator 260 of a predetermined frequency and a first counter 265 for providing internal timing to said electronic system, said electronic system converting itself into said low-power stop mode after a predetermined period of inactivity, said low-power stop mode causing said electronic system to remain non-operational until said stop mode is terminated, comprising: a second oscillator 210 of a nominal predetermined frequency for continuously generating an oscillating signal in said low-power stop mode, said second oscillator 210 being less accurate than said first oscillator 260; a second counter 220 coupled to said second oscillator 210 for counting said oscillating signal to a predetermined count until said second counter expires in said predetermined time period; detection means coupled to said second counter 220 for detecting if said second counter has expired and if so, said detection means generating a wakeup signal to invoke said wakeup logic 270, such that said stop mode is terminated after said predetermined time period.
Claim 3
Dependent Claim
99 words
A device according to Claim 2 , further comprising: a calibration means coupled to said second oscillator 210 and to said first oscillator 260, said calibration means, operative after said stop mode is terminated, causing said first counter 265 to count using said first oscillator 260, after said first oscillator 260 is out of said stop mode, with said second counter 220 also counting using said second oscillator 210, said calibration means determining a true operating frequency of said second oscillator 210 and setting said predetermined time period according to said true operating frequency of said second oscillator 210.
Claim 4
Dependent Claim
93 words
A device according to Claim 3 , wherein said calibration means: synchronizing said second counter 220 with said first counter 265 in a normal operating mode; said first counter 265 continuously counting said first oscillator 260 until said second counter 220 has expired; reading said first counter 265 to determine the time it took said second counter 220 to expire; calculating said true operating frequency of said second oscillator 210 based on said time it took said second counter 220 to expire and said predetermined count initially set in said second counter 220.
Claim 5
Independent Claim
188 words
A device for invoking a wakeup logic 270 of a processing device in a packet radio communication system from a low-power stop mode after a predetermined time period, said packet radio communication system comprising a first oscillator 260 of a predetermined frequency and a first counter 265 for providing internal timing to said communication system, said packet radio communication system converting itself into said low-power stop mode after a predetermined period of inactivity, said low-power stop mode causing said packet radio communication system to remain non-operational until said stop mode is terminated, comprising: a second oscillator 210 of a nominal predetermined frequency for continuously generating an oscillating signal in said low-power stop mode; a second counter 220 coupled to said second oscillator 210 for counting said oscillating signal to a predetermined count until said second counter 220 expires in said predetermined time period; detection means coupled to said second counter 220 for detecting if said second counter 220 has expired and if so, said detection means generating a wakeup signal to invoke said wakeup logic 270, such that said stop mode is terminated after said predetermined time period.
Claim 6
Dependent Claim
99 words
A device according to Claim 5 , further comprising: a calibration means coupled to said second oscillator 210 and to said first oscillator 260, said calibration means, operative after said stop mode is terminated, causing said first counter 265 to count using said first oscillator 260, after said first oscillator 260 is out of said stop mode, with said second counter 220 also counting using said second oscillator 210, said calibration means determining a true operating frequency of said second oscillator 210 and setting said predetermined time period according to said true operating frequency of said second oscillator 210.
Claim 7
Dependent Claim
344 words
In a processor-based packet radio interfacing between a data processing unit and a wireless data transceiver, said packet radio comprising a first oscillator 260 and a first timer for providing internal timing and a wakeup logic 270 for invoking said packet radio from a stop mode, said stop mode causing said packet radio to remain non-operational after said packet radio has been inactive in a predetermined period to preserve power, a low-power device for periodically triggering said wakeup logic 270 to invoke said packet radio from said stop mode, comprising: a ring oscillator 210 of a predetermined frequency for continuously generating an oscillating signal in said stop mode; a second counter 220 coupled to said second oscillator 210 for counting said second oscillator 210 to a predetermined count when said second counter 220 expires corresponding to a predetermined period for said packet radio to awake from said stop mode; detection means coupled to said second counter 220 for detecting if said second counter 220 has expired and if so, said detection means generating a wakeup signal to trigger said wakeup logic 270, such that stop mode is terminated after said predetermined period; a calibration means coupled to said second oscillator 210 and to said first oscillator 260, said calibration means, operative after said stop mode is terminated, operating said first and second counters 265, 220 to determine an actual time it took said second counter to expire and setting said predetermined period for triggering said wakeup logic 270 according to said actual time of said second oscillator 210, said calibration means: synchronizing said second counter 220 with said first counter 265 after said stop mode is terminated; said first counter 265 continuously counting said first oscillator 260 until said second counter 220 has expired; reading said first counter 265 to determine the time it took said second counter 220 to expire; calculating said true operating frequency of said second oscillator 210 based on said time it took said second counter 220 to expire and said predetermined count initially set in said second counter 220.
Claim 8
Independent Claim
195 words
A method for a processing unit in an electronic system to self-awaken from a low-power stop mode after a predetermined time period, said electronic system comprising a second oscillator 210 of a nominal frequency and a crystal oscillator 260 of a predetermined frequency and a first counter 265 for providing internal timing to said electronic system, said electronic system converting itself into said low-power stop mode from a normal operating mode after a predetermined period of inactivity, said low-power stop mode causing said electronic system to remain non-operational until said stop mode is terminated, comprising the steps of: a) continuously operating said second oscillator 210 to generate an oscillating signal in said low-power stop mode; b) counting said oscillating signals by using a second counter 220 coupled to said second oscillator 210 to a predetermined count when said second counter 220 expires in said predetermined time period; c) detecting by using a detection means coupled to said second counter 220 if said second counter 220 has expired and if so, said detection means generating a wakeup signal to invoke said wakeup logic 270, such that said stop mode is terminated after said predetermined time period.
Claim 9
Dependent Claim
105 words
The method according to Claim 8 , further comprising the step of: d) calibrating by using a calibration means coupled to said second oscillator 210 and to said crystal oscillator 260, said calibration means operative after said stop mode is terminated, causing said first counter to count using said crystal oscillator 260, after said crystal oscillator 260 is out of said stop mode, with said second counter 220 also counting using said second oscillator 210, said calibration means determining a true operating frequency of said second oscillator 210 and setting said predetermined time period according to said true operating frequency of said second oscillator 210.
Claim 10
Independent Claim
203 words
A method for a data/voice communication system to self-awaken from a low-power stop mode after a predetermined time period to receive an asynchronous paging signal from a basestation, said data/voice communication system comprising a second oscillator 210 of a nominal frequency and a crystal oscillator 260 of a predetermined frequency and a first counter 265 for providing internal timing to said electronic system, said data/voice communication system converting itself into said low-power stop mode from a normal operating mode after a predetermined period of inactivity, said low-power stop mode causing said electronic system to remain dormant until said stop mode is terminated, comprising the steps of: a) continuously operating said second oscillator 210 to generate an oscillating signal in said low-power stop mode; b) counting said oscillating signals by using a second counter 220 coupled to said second oscillator 210 to a predetermined count when said second counter 220 expires in said predetermined time period; c) detecting by using a detection means coupled to said second counter 220 if said second counter 220 has expired and if so, said detection means generating a wakeup signal to invoke said wakeup logic 270, such that said stop mode is terminated after said predetermined time period.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.