EP0750258A2
Expired / Lapsed
EP
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Memory state recovering apparatus
Assignee: Toshiba Corp
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Filing: 1996-06-18
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Granted: —
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Expires: 2016-06-18
Abstract
Abstract In a memory state recovering apparatus, processors (10-1 to 10-n) process data and a main memory (17) holds data necessary for the data processing at the processors (10-1 to 10-n). Caches (12-1 to 12-n) are provided to correspond to the processors (10-1 to 10-n) and have the function of issuing an invalidation transaction to specify the invalidation of the data to maintain the consistency of the data. A before image buffer (18) combines an address in the main memory (17) with the data held in the location indicated by the address and stores the combination. A memory access control section (14) stores in the buffer memory the address targeted in the main memory and the data stored in the location indicated by the address in accordance with the invalidation transaction issued from the caches (12-1 to 12-n). With this configuration, the time required for a checkpoint process can be shortened, thereby improving the system performance.
Inventors
- 👤 Yoshio c/o Intellectual Property Div. Masubuchi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 05:42
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/14; G06F11/1402; G06F11/1405; G06F11/1407; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
142 words
A memory state recovering apparatus comprising: at least one processor (10) capable of processing data; at least one copy-back cache (12) that is provided to correspond to said processor and issues various transactions in accordance with an access request of said processor, and that has a data consistency maintenance function; a main memory (17) for holding data necessary for the data processing at said processor; and a buffer memory (18) for storing a set of the data in said main memory before update and its address, characterized by further comprising memory access control means (14) responsive to a transaction issued from the cache when said processor has made a write access request to the corresponding cache, storing in said buffer memory the set of the address and corresponding data which has held in said main memory and is targeted by the transaction.
Claim 2
Dependent Claim
45 words
An apparatus according to claim 1, characterized in that said memory access control means (14) includes checkpoint execution means for storing the internal state of said processor and the data in said cache in a modified state in said main memory at predetermined time intervals.
Claim 3
Dependent Claim
19 words
An apparatus according to claim 1, characterized in that said buffer memory (18) is provided in said main memory.
Claim 4
Dependent Claim
163 words
A memory state recovering apparatus comprising: a bus (16); a plurality of processors (10) capable of processing data; a plurality of copy-back caches (12) that are connected to each other via said bus and provided to correspond to said processors and issue various transactions in accordance with access requests of said processors, and that have a data consistency maintenance function; a main memory (17) for holding data necessary for the data processing at said processors; and a buffer memory (18) for storing a set of the data in said main memory before update and its address, characterized by further comprising memory access control means (14) that is connected to said bus and responsive to a transaction issued from the cache when one of said plurality of processors has made a write access request to the corresponding cache, storing in said buffer memory the set of the address and corresponding data which has held in said main memory and is targeted by the transaction.
Claim 5
Dependent Claim
49 words
An apparatus according to claim 4, characterized in that said memory access control means (14) includes checkpoint execution means for storing the internal states of said plurality of processors and the data in said plurality of caches in a modified state in said main memory at predetermined time intervals.
Claim 6
Dependent Claim
25 words
An apparatus according to claim 4, characterized in that said memory access control means (14) includes means for snooping various transactions issued onto said bus.
Claim 7
Dependent Claim
66 words
An apparatus according to claim 4, characterized in that said memory access control means (14) includes means for, when the transaction issued from said cache is an invalidation transaction to specify the invalidation of the corresponding cache lines in other processors, reading from the main memory the address and corresponding data in said main memory indicated by the transaction and storing them in said buffer memory.
Claim 8
Dependent Claim
97 words
An apparatus according to claim 7, characterized in that said memory access control means (14) includes means for, when the transaction issued from said cache is a read invalidation transaction to specify not only the reading of the data from the main memory or the corresponding cache lines in other processors but also the invalidation of the corresponding cache lines in the other processors, reading the address and corresponding data in said main memory indicated by the transaction or the data on the corresponding cache lines of the other processors and storing them in said buffer memory.
Claim 9
Dependent Claim
19 words
An apparatus according to claim 4, characterized in that said buffer memory (18) is provided in said main memory.
Claim 10
Dependent Claim
144 words
In a memory state recovering apparatus comprising at least one processor (10) capable of processing data, at least one copy-back cache (12) that is provided correspond to said processor and issues various transactions in accordance with an access request of said processor and that has a data consistency maintenance function, a main memory (17) for holding data necessary for the data processing at said processor, and a buffer memory (18) for storing a set of the data in said main memory before update and its address, a memory access control method characterized by comprising the steps of: detecting a transaction issued from the cache when said processor has made a write access request to the corresponding cache; and storing in said buffer memory the set of the address and corresponding data which has held in said main memory and is targeted by the transaction.
Claim 11
Dependent Claim
38 words
A method according to claim 10, characterized by further comprising the step of storing the internal state of said processor and the data in said cache in a modified state in said main memory at predetermined time intervals.
Claim 12
Dependent Claim
159 words
In a memory state recovering apparatus comprising a bus (16), a plurality of processors (10) capable of processing data, a plurality of copy-back caches (12) that are connected to each other via said bus and provided to correspond to said processors and issue various transactions in accordance with access requests of said processors and that have a data consistency maintenance function, a main memory (17) for holding data necessary for the data processing at said processors, and a buffer memory (18) for storing a set of the data in said main memory before update and its address, a memory access control method characterized by comprising the steps of: detecting a transaction issued from the cache when one of said plurality of processors has made a write access request to the corresponding cache; and storing in said buffer memory the set of the address and corresponding data which has held in said main memory and is targeted by the transaction.
Claim 13
Dependent Claim
42 words
A method according to claim 12, characterized by further comprising the step of storing the internal states of said plurality of processors and the data in said plurality of caches in a modified state in said main memory at predetermined time intervals.
Claim 14
Dependent Claim
23 words
A method according to claim 12, characterized in that said detecting step includes the step of snooping various transactions issued onto said bus.
References Cited (Backward Citations)
No citation records indexed.
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