High read speed multivalued read only memory device

Claim 2

A four-valued read only memory device including at least one memory cell transistor, accessed by an address comprising: first outputting means for applying a first voltage (V2) to a gate of said memory cell transistor and outputting a first output signal indicating whether said memory cell transistor is turned ON or OFF; and second outputting means for individually applying said first voltage, and second and third voltages (V1, V3) to the gate of said memory cell transistor and outputting a second output signal in accordance with whether said memory cell transistor is turned ON or OFF when said first voltage is applied to the gate of said memory cell, whether said memory cell transistor is turned ON or OFF when said second voltage is applied to the gate of said memory cell, and whether said memory cell transistor is turned ON or OFF when said third voltage is applied to the gate of said memory cell, said first outputting means being operated when said address indicates a first value, said second outputting means being operated when said address indicates a second value.

Claim 3

The device as set forth in claim 2, wherein said first voltage is between said second voltage and said third voltage.

Claim 4

The device as set forth in claim 2, wherein said first outputting means comprises first storing means (608) for storing information indicating whether said memory cell transistor is turned ON or OFF when said first voltage is applied to the gate of said memory cell transistor, an output of said first storing means being output as said first output signal, said second outputting means comprising: second storing means (603) for storing information indicating whether said memory cell transistor is turned ON or OFF when said first voltage is applied to the gate of said memory cell transistor; third storing means (602) for storing information indicating whether said memory cell transistor is turned ON or OFF when said second voltage is applied to the gate of said memory cell transistor; fourth storing means (604) for storing information indicating whether said memory cell transistor is turned ON or OFF when said third voltage is applied to the gate of said memory call transistor; and a logic circuit (605), connected to said second, third and fourth storing means, for performing a logic operation upon information stored in said second, third and fourth storing means, an output of said logic circuit being output as said second output signal.

Claim 5

A four-valued read only memory device comprising: a plurality of word lines (WL0, WL1, ···); a plurality of digit lines (DL0, DL1, ···); a plurality of memory cell transistors (C (0, 0), C (0, 1), ···) provided at intersections between said word lines and said digit lines, each of said memory cell transistors having one of first, second, third and fourth threshold voltages (VT0, VT1, VT2, VT3), said first threshold voltage being lower than said second threshold voltage, said second threshold voltage being lower than said third threshold voltage, said third voltage being lower than said fourth voltage; an address decoder (1') for selecting one of said word lines in accordance with a first part (X1, X2, ···, Xm) of an address; first means for applying a first voltage (V2) between said second and third threshold voltages to the one of said word lines when a second part (X0) of said address indicates a first value; second means for individually applying said first voltage, a second voltage (V1) between said first and second threshold voltages and a third voltage (V3) between said third and fourth threshold voltages to the one of said word lines when the second part of said address indicates a second value; a plurality of determination circuits (2'-0, 2'-1, ···), each connected to one of said digit lines, for generating output signals (D0, D1, ···) in accordance with voltages at said digit lines.

Claim 6

The device as set forth in claim 5, further comprising an address counter (4), connected to said address decoder, for incrementing said address.

Claim 7

A four-valued read only memory device comprising: a plurality of word lines (WL0, WL1, ···); a plurality of digit lines (DL0, DL1, ···); a plurality of memory cell transistors (C (0, 0), C (0, 1), ···) provided at intersections between said word lines and said digit lines, each of said memory cell transistors having one of first, second, third and fourth threshold voltages (VT0, VT1, VT2, VT3), said first threshold voltage being lower than said second threshold voltage, said second threshold voltage being lower than said third threshold voltage, said third voltage being lower than said fourth voltage; an address counter (4) for receiving an external address (X1 ∼ Xm) and an internal address bit (X0) to sequentially generate an internal address (X1 ∼ Xm); an address decoder (1'), connected to said address counter, for selecting one of said word lines in accordance with of said internal address; first means for applying a first voltage (V2) between said second and third threshold voltages to the one of said word lines when said internal address bit internal indicates a first value; second means for individually applying a second voltage (V1) between said first and second threshold voltages and a third voltage (V3) between said third and fourth threshold voltages to the one of said word lines when the said internal address bit indicates a second value; a plurality of determination circuits (2'-0, 2'-1, ···), each connected to one of said digit lines, for generating output signals (D0, D1, ···) in accordance with voltages at said digit lines.

Claim 8

The device as set forth in claim 7, wherein said determination circuits generate said output signals in accordance with only information indicating whether the voltage at said digit lines are high or low when said first voltage is applied to the one of said word lines, when said internal address bit indicates the first value, said determination circuits generating said output signals in accordance with information indicating whether the voltage at said digit lines are high or low when said first voltage is applied to the one of said word lines, information indicating whether the voltage at said digit lines are high or low when said second voltage is applied to the one of said word lines, and information indicating whether the voltage at said digit lines are high or low when said third voltage is applied to the one of said word lines, when said internal address bit indicates the second value.