Patent US1349761A successfully refreshed from Google Patents.
Patent US2068450A successfully refreshed from Google Patents.
EP0731494A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Method for fabricating an integrated circuit using boron implant methodology
Assignee: GlobalFoundries Inc
•
Filing: 1996-03-06
•
Granted: —
•
Expires: 2016-03-06
Abstract
Abstract A semiconductor structure with large tilt angle boron implant is provided for reducing threshold shifts or rolloff at the channel edges. By minimizing threshold shifts, short channel effects and subthreshold currents at or near the substrate surface are lessened. The semiconductor structure is prepared by implanting boron at a non-perpendicular angle into the juncture between the channel and the source/drain as well as the juncture between the field areas and the source/drain. Placement of boron into these critical regions replenishes segregating and redistributing threshold adjust implant species and channel stop implant species resulting from process temperature cycles. Using lighter boron ions allow for a lesser annealing temperature and thereby avoids the disadvantages of enhanced redistribution and diffusion caused by high temperature anneal.
Inventors
- 👤 Mohammed Anjum
- 👤 Klaus H. Koop
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 16:00
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/21; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D30/601; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/518; H10P30/202; H10P30/204; H10P30/222
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
78 words
A method for fabricating an integrated circuit comprising: providing an opening to an active region of a semiconductor substrate upper surface; implanting boron ions at an angle substantially perpendicular to said semiconductor substrate upper surface through said opening and into said active region; patterning a polysilicon trace element upon a portion of said active region; and implanting boron ions at a non-perpendicular angle relative to said semiconductor substrate upper surface through said opening and into said active region.
Claim 2
Dependent Claim
56 words
The method as recited in claim 1, wherein said first implanting step comprises injecting boron ions to a concentration peak density at a first depth below said semiconductor substrate upper surface, and wherein said second implanting step comprises injecting boron ions to a concentration peak density at a second depth below said semiconductor substrate upper surface.
Claim 3
Dependent Claim
17 words
The method as recited in claim 2, wherein said first depth is greater than said second depth.
Claim 4
Dependent Claim
27 words
The method as recited in claim 1, wherein said second implanting step comprises injecting a set of said boron ions into said active region beneath said polysilicon.
Claim 5
Dependent Claim
22 words
The method as recited in claim 1, subsequent to said second implanting step, further comprising implanting n-type ions into said active region.
Claim 6
Dependent Claim
18 words
The method as recited in claim 5, wherein said n-type ions are of larger atomic mass than boron.
Claim 7
Dependent Claim
14 words
The method as recited in claim 5, wherein said n-type ions are arsenic ions.
Claim 8
Dependent Claim
90 words
The method as recited in claim 1, wherein said providing step comprises growing a pad oxide upon said semiconductor substrate upper surface, depositing silicon nitride upon said pad oxide, selectively removing a portion of said silicon nitride and said pad oxide to expose a field region of said semiconductor substrate upper surface, forming an insulation material upon the exposed field region of said semiconductor substrate upper surface, and removing the remaining said silicon nitride and said pad oxide overlying said active region to produce said opening through the insulation material.
Claim 9
Dependent Claim
31 words
The method as recited in claim 8, wherein said second implanting step further comprising injecting a set of said boron ions into said semiconductor substrate upper surface beneath said insulation material.
Claim 10
Dependent Claim
10 words
An integrated circuit fabricated by the method of claim 1.
Claim 11
Independent Claim
168 words
A method for replenishing diffusion and segregation of boron from a channel region and from a field region to adjacent source and drain regions in order to reduce drain induced barrier lower-induced currents, the method comprising the steps of: providing boron into a field region, wherein the field region is a portion of a semiconductor substrate residing below a patterned insulation material; providing boron into a channel region laterally spaced from said field region, wherein said channel region resides within said substrate below a patterned polysilicon trace element; implanting boron ions into a portion of said channel region at a non-perpendicular angle relative to said semiconductor substrate, wherein a set of said implanted boron ions reside at a first concentration peak density within said channel region and said field region; and implanting arsenic ions into a source and drain region, wherein said implanted arsenic ions reside at a second concentration peak density, and wherein the source and drain region resides between said field region and said channel region.
Claim 12
Dependent Claim
31 words
The method as recited in claim 11, wherein said first concentration peak density is shallower in relation to an upper surface of said semiconductor substrate than said second concentration peak density.
Claim 13
Dependent Claim
24 words
The method as recited in claim 11, wherein said non-perpendicular angle is an acute angle relative to an upper surface of said semiconductor substrate.
Claim 14
Dependent Claim
14 words
The method as recited in claim 11, wherein said insulation material comprises silicon dioxide.
Claim 15
Dependent Claim
10 words
An integrated circuit fabricated by the method of claim 11.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.