Patent US6180978B1 successfully refreshed from Google Patents.
EP0730307A2
Expired / Lapsed
EP
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FET technology with dielectrically isolated sources and drains
Assignee: STMicroelectronics lnc USA
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Filing: 1996-02-26
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Granted: —
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Expires: 2016-02-26
Abstract
Abstract A field-effect transistor structure wherein a single patterned thin film semiconductor layer: is monocrystalline, and epitaxially matched to an underlying body region, in channel locations; and is polycrystalline in source/drain locations which abut said channel locations.
Inventors
- 👤 Richard A. Blanchard
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 13:14
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/027; H10D30/0278; H10D30/031; H10D30/0321; H10D30/0323; H10D30/60; H10D30/67; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6744; H10D30/6758; H10D62/00; H10D62/10; H10D62/113; H10D62/115; H10D62/116; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/292; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0167; H10D84/017; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/854; H10D86/00; H10D86/01
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
186 words
A method for fabricating integrated circuit devices, comprising the steps of: (a.) providing a substrate which includes at least one substantially monolithic body of semiconductor material; (b.) covering part of the surface of said monolithic body with a patterned dielectric layer, said patterned dielectric layer leaving said monolithic body exposed in transistor channel locations; (c.) forming additional semiconductor material, as monocrystalline semiconductor material on said monolithic body in said transistor channel locations, and as polycrystalline semiconductor material elsewhere; said semiconductor material being formed to a thickness which is greater than the thickness of said patterned dielectric layer; (d.) patterning said additional material to form a patterned thin film layer, and forming a gate dielectric on said additional material; (e.) forming an additional patterned conductive thin film layer on said gate dielectric; (f.) implanting dopants of a desired conductivity type into said additional material where exposed by said additional patterned conductive thin film layer; whereby monocrystalline portions of said additional material beneath said additional patterned conductive thin film layer form transistor channel regions, and polycrystalline portions of said additional material provide source and drain regions adjacent thereto.
Claim 2
Independent Claim
194 words
A method for fabricating integrated circuit devices, comprising the steps of: (a.) providing a substrate which includes at least one substantially monolithic body of semiconductor material; (b.) covering part of the surface of said monolithic body with a patterned dielectric layer, said patterned dielectric layer leaving said monolithic body exposed in transistor channel locations; (c.) depositing additional semiconductor material overall, as epitaxially matched monocrystalline semiconductor material on said monolithic body in said transistor channel locations, and as polycrystalline semiconductor material elsewhere; said semiconductor material being formed to a thickness which is greater than the thickness of said patterned dielectric layer; (d.) patterning said additional material to form a patterned thin film layer, and forming a gate dielectric on said additional material; (e.) forming an additional patterned conductive thin film layer, comprising polycrystalline semiconductor material, on said gate dielectric; and (f.) implanting dopants of a desired conductivity type into said additional material where exposed by said additional patterned conductive thin film layer; whereby monocrystalline portions of said additional material beneath said additional patterned conductive thin film layer form transistor channel regions, and polycrystalline portions of said additional material provide source and drain regions adjacent thereto.
Claim 3
Independent Claim
228 words
A method for fabricating CMOS integrated circuit devices, comprising the steps of: (a.) providing a substrate which includes at least one substantially monolithic body of semiconductor material, having at least one first-conductivity-type surface region and at least one second-conductivity-type surface region; (b.) covering part of the surface of said monolithic body with a patterned dielectric layer, said patterned dielectric layer leaving said monolithic body exposed in transistor channel locations; (c.) forming additional semiconductor material, as monocrystalline semiconductor material on said monolithic body in said transistor channel locations, and as polycrystalline semiconductor material elsewhere; said semiconductor material being formed to a thickness which is greater than the thickness of said patterned dielectric layer; (d.) patterning said additional material to form a patterned thin film layer, and forming a gate dielectric on said additional material; (e.) forming an additional patterned conductive thin film layer on said gate dielectric; (f.) implanting dopants of said first conductivity type over locations of said second-conductivity-type regions of said body, and implanting dopants of said second conductivity type over locations of said first-conductivity-type regions of said body, to dope said additional material where exposed by said additional patterned conductive thin film layer; whereby monocrystalline portions of said additional material beneath said additional patterned conductive thin film layer form transistor channel regions, and polycrystalline portions of said additional material provide source and drain regions adjacent thereto.
Claim 4
Independent Claim
16 words
The method of any one of claims 1 to 3, wherein said semiconductor material is silicon.
Claim 5
Independent Claim
24 words
The method of any one of claims 1 to 3, wherein said patterned dielectric layer and said gate dielectric both consist of silicon dioxide.
Claim 6
Independent Claim
34 words
The method of any one of claims 1 to 3, further comprising the additional step of forming a sidewall spacer on said additional patterned conductive thin film layer prior to said implanting step (f).
Claim 7
Independent Claim
27 words
The method of any one of claims 1 to 3, further comprising the additional step of doping said additional semiconductor material prior to said forming step (e).
Claim 8
Independent Claim
36 words
The method of any one of claims 1 to 3, further comprising the additional step of forming at least one first-conductivity-type surface region and at elast one second-conductivity-type surface region prior to said covering step (b).
Claim 9
Independent Claim
41 words
The method of any one of claims 1 to 3, further comprising the additional step of forming a patterned thick field dielectric region, which is more than twice as thick as said patterned dielectric layer, prior to said covering step (b).
Claim 10
Dependent Claim
83 words
An integrated circuit field-effect transistor structure, comprising: a monocrystalline semiconductor channel region; a conductive gate capacitively coupled to said channel region; a monocrystalline semiconductor body region which underlies and is epitaxially continuous with said channel region; first and second polycrystalline semiconductor source/drain regions which laterally adjoin opposing sides of said channel region, and each extend continuously therefrom; and a patterned dielectric layer, which underlies said source/drain regions but not said channel region; said patterned dielectric layer being thinner than said semiconductor source/drain regions.
References Cited (Backward Citations)
No citation records indexed.
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