EP0726575A2
Expired / Lapsed
EP
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Semiconductor integrated circuit device
Assignee: International Business Machines Corp
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Filing: 1996-01-23
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Granted: —
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Expires: 2016-01-23
Abstract
Abstract A DRAM macro cell 14 integrated together with a logic cell on the same chip comprises a guard ring 26 surrounding the memory forming area, memory cell arrays 42, a power supply line 34, a ground line 36, additional ground lines 38, and by-pass capacitors 70 connected between the power supply line 34 and the ground line 36. The power supply line 34 is connected to a power supply pad different from the power supply pad to which the power supply line of the logic cell is connected, and the ground line 36 and the ground line of the logic cell are connected to common ground pads or proximate grounding pads interconnected by low-impedance lines. The additional ground lines 38 are connected to the substrate to stabilize substrate potential. This provides a high-density semiconductor integrated circuit device which is reliable and enables high-speed operation by forming DRAM macro cells and logic cell on the same chip.
Inventors
- 👤 Hisatada Miyatake
- 👤 Toshio Sunaga
- 👤 Koji Kitamura
- 👤 Masaaki Yamamoto
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 13:00
CPC Classifications
H; H10; H10B; H10B12/00; G; G11; G11C; G11C5/00; G11C5/14
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
113 words
A semiconductor integrated circuit device in which a logic block and a memory block connected to the logic block are formed on a semiconductor substrate of the same chip with power supply pads, ground pads and signal pads being formed thereon, the device being characterised by: the memory block including an array of DRAM memory cells, a power supply line and a ground line, each of the memory cells including a memory capacitor; the logic block including a logic circuit, a power supply line, and a ground line; and the power supply line of the memory block and the power supply line of the logic block being connected to different power supply pads.
Claim 2
Dependent Claim
49 words
The semiconductor integrated circuit device according to Claim 1, wherein the ground line of the memory block and the ground line of the logic block are connected to the same ground pad or different ground pads which are close to each other and interconnected through a low impedance line.
Claim 3
Dependent Claim
68 words
The semiconductor integrated circuit device according to Claims 1 or 2, wherein the chip includes an off-chip driver circuit provided with a power supply line and a ground line, and the power supply line of the off-chip driver circuit is connected to a power supply pad different from the power supply pad to which the power supply lines of the memory block and the logic block are connected.
Claim 4
Dependent Claim
64 words
The semiconductor integrated circuit device according to Claims 1 or 2, wherein the chip includes an off-chip driver circuit provided with a power supply line and a ground line, and the ground line of the off-chip driver circuit is connected to a ground pad different from the ground pad to which the ground lines of the memory block and the logic block are connected.
Claim 5
Dependent Claim
66 words
The semiconductor integrated circuit device according to Claims 1 or 2, wherein the chip includes a receiver circuit provided with a power supply line and a ground line, and the power supply line of the receiver circuit is connected to a power supply pad different from the power supply pad to which the power supply lines of the memory block and the logic block are connected.
Claim 6
Dependent Claim
71 words
The semiconductor integrated circuit device according to Claims 1 or 2, wherein the chip includes a receiver circuit provided with a power supply line and a ground line, and the ground line of the receiver circuit is connected to the same ground pad to which the ground line of the logic block is connected or different ground pads which are close to each other and interconnected through a low impedance line.
Claim 7
Dependent Claim
73 words
The semiconductor integrated circuit device according to Claims 1 or 2, wherein the chip includes an additional power supply line or ground line connected to a predetermined power supply pad or ground pad but not connected to the internal circuit of the memory block, and the additional power supply line or ground line is connected to the semiconductor substrate at a plurality of locations to stabilize the electric potential of the semiconductor substrate.
Claim 8
Dependent Claim
145 words
A semiconductor integrated circuit device in which a logic block and a memory block connected to the logic block are formed on a semiconductor substrate of the same chip with power supply pads, ground pads and signal pads being formed thereon, the device being characterised by: the memory block including an array of a plurality of DRAM macro cells, each of the DRAM macro cells including one or more DRAM memory cell arrays, peripheral circuits required for read and write operations of the one or more DRAM memory arrays, a power supply line and a ground line, and the semiconductor substrate including a guard ring of the opposite conductivity type to that of the semiconductor substrate, the guard ring being formed to surround a region including the one or more DRAM memory cell arrays and the peripheral circuits of each of the DRAM macro cells.
Claim 9
Dependent Claim
86 words
The semiconductor integrated circuit device according to Claim 8, wherein the semiconductor substrate is of P conductivity type, the guard ring is of N conductivity type, and the power supply line of each of the DRAM macro cells is formed in the shape of a frame to surround a region including the one or more DRAM memory cell arrays and the peripheral circuits of the DRAM macro cell and to positionally overlap with the guard ring, the power supply line being connected to the guard ring.
Claim 10
Dependent Claim
84 words
The semiconductor integrated circuit device according to Claim 8, wherein the semiconductor substrate is of N conductivity type, the guard ring is of P conductivity type, and the ground line of each of the DRAM macro cells is formed in the shape of a frame to surround a region including the one or more DRAM memory cell arrays and the peripheral circuits of the DRAM macro cell and to positionally overlap with the guard ring, the ground line being connected to the guard ring.
Claim 11
Dependent Claim
48 words
The semiconductor integrated circuit device according to either one of Claims 8, 9, and 10, wherein the memory cell comprises a field effect transistor and a capacitor, and the field effect transistor is formed in a well of the opposite conductivity type to that of the semiconductor substrate.
Claim 12
Dependent Claim
35 words
The semiconductor integrated circuit device according to Claim 11, wherein each of the DRAM macro cells includes a by-pass capacitor connected between the power supply line and the ground line of the DRAM macro cell.
Claim 13
Dependent Claim
23 words
The semiconductor integrated circuit device according to Claim 12, wherein the capacitor of the memory cell and the by-pass capacitor are trench-type capacitors.
References Cited (Backward Citations)
No citation records indexed.
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