Semiconductor device having an improved trench isolation and method for forming the same

Claim 1

A trench isolation structure comprising : a semiconductor region (1) ; a first insulation film (5, 16) formed on a top surface of said semiconductor region (1) ; a trench groove (11) extending vertically from said first insulation film (5, 16) into said semiconductor region (1) so that a bottom of said trench groove lies below an interface between said first insulation film (5, 16) and said semiconductor region (1) ; characterized in that an inter-layer insulator (13) is provided which resides not only on said first insulation film (5, 16) but also within said trench groove so that said inter-layer insulator (13) fills up said trench groove (11).

Claim 21

A method for forming a trench isolation in a semiconductor region (1), said method comprising the steps of : forming a first insulation film (5, 16) on a top surface of a semiconductor region (1) ; selectively forming a trench groove (11) extending vertically from said first insulation film (5, 16) into said semiconductor region (1) so that a bottom of said trench groove (11) lies below an interface between said first insulation film (5, 16) and said semiconductor region (1) ; and forming an inter-layer insulator (13) which resides not only on said first insulation film (5, 16) but also within said trench groove (11) so that said inter-layer insulator (13) fills up said trench groove.

Claim 22

A method for forming a trench isolation structure in a silicon region, said method comprising the steps of : forming a first insulation film (5, 16) on a top surface of a silicon region (1) ; selectively forming a trench groove (11) extending vertically from said first insulation film (5, 16) to said silicon region (1) so that a bottom of said trench groove (11) lies below an interface between said first insulation film (5, 16) and said silicon region (1) ; forming a second insulation film (12) which extends at least on vertical side walls and a bottom wall of said trench groove (11) ; selectively forming a polysilicon film (10a) on said second insulation film (12) except on its upper portion so that said polysilicon film (10a) fills with said trench groove (11) expect for its upper region ; and forming an inter-layer insulator (13) which resides not only on said first insulation film (5, 16) but also on said polysilicon film (10a) so that said inter-layer insulator (13) fills up said upper region of said trench groove.

Claim 23

A method for forming a bipolar transistor with trench isolations comprising the steps of : forming a buried layer (2) on a silicon substrate (1) ; forming an epitaxial layer (3) on said buried layer (2) ; forming a first insulation film (5, 16) on a top surface of said epitaxial layer (3), said first insulation film (5, 16) comprising at least one thin film portion and at least two thick field oxide film portions (5) sandwiching said at least one thin oxide film (16) portion ; selectively forming a base region (7) in an upper region of said epitaxial layer (3) and under said thin oxide film portion ; selectively forming an emitter region (10b) in an upper region of said base region (7) and an emitter plug electrode (10) on said emitter region (10b) ; selectively forming at least one trench groove (11) extending vertically from said first insulation film (5, 16) through said epitaxial layer (3) and said buried layer (2) into said silicon substrate (1) ; and forming an inter-layer insulator (13) both over said first insulation film (5, 16) and above said emitter plug electrode (10) and within said trench groove (11) so that said inter-layer insulator (13) fills up said trench groove.

Claim 24

A method for forming a bipolar transistor with trench isolations comprising : forming a buried layer (2) on a silicon substrate (1) ; forming an epitaxial layer (3) on said buried layer (2) ; forming a first insulation film (5, 16) on a top surface of said epitaxial layer (3), said first insulation film (5, 16) comprising at least one thin oxide film portion and at least two thick field oxide film portions (5) sandwiching said at least one thin oxide film (16) ; selectively forming a base region (7) in an upper region of said epitaxial layer (3) and under said at least one thin oxide film (16) ; selectively forming an emitter region (10b) in an upper region of said base region (7) and an emitter plug electrode (10) on said emitter region (10b) ; selectively forming at least one trench groove (11) extending vertically from said first insulation film (5, 16) through said epitaxial layer (3) and said buried layer (2) into said silicon substrate (1) ; forming a second insulation film (12) which extend at least on vertical side walls and a bottom wall of said trench groove (11) ; selectively forming a polysilicon film (10a) on said second insulation film (12) except on its upper portion so that said polysilicon film (10a) fills with said trench groove (11) except for its upper region ; and forming an inter-layer insulator (13) which resides not only on said first insulation film (5, 16) but also on said polysilicon film (10a) so that said inter-layer insulator (13) fills up said upper region of said trench groove.

Claim 25

A method for forming a MOS field effect transistor with a trench isolation comprising the steps of : forming an impurity doped well region (30, 31) on a silicon substrate (1) ; forming a first insulation film (5, 16) on a top surface of said impurity doped well region (30, 31), said first insulation film (5, 16) comprising at least one thick field oxide film portion (5) and at least two thin oxide film portions sandwiching said at least one thick field oxide film portion (5) ; selectively forming at least two gate electrodes (32) on said at least two thin film portions ; selectively forming source/drain diffusion regions (33, 34) in an upper region of said impurity doped well region (30, 31) and under each of said thin oxide film portions, said source/drain diffusion regions (33, 34) sandwiching each of at least two channel regions under said at least two gate electrodes (32) ; selectively forming a trench groove (11) extending vertically from said thick field oxide film portion (5) through said impurity doped well region (30, 31) into said silicon substrate (1) ; and forming an inter-layer insulator (13) not only over said first insulation film (5, 16) and above said gate electrode but also within said trench groove (11) so that said inter-layer insulator (13) fills up said trench groove.

Claim 26

A method for forming a MOS field effect transistor with a trench isolation comprising the steps of : forming an impurity doped well region (30, 31) on a silicon substrate (1) ; forming a first insulation film (5, 16) on a top surface of said impurity doped well region (30, 31), said first insulation film (5, 16) comprising at least one thick field oxide film portion (5) and at least two thin oxide film portions sandwiching said at least one thick field oxide film portion (5) ; selectively forming at least two gate electrodes (32) on said at least two thin film portions respectively ; selectively forming source/drain diffusion regions (33, 34) in an upper region of said impurity doped well region (30, 31) and under each of said thin oxide film portions, said source/drain diffusion regions (33, 34) defining each of at least two channel regions under each of said at least two gate electrodes (32) ; selectively forming a trench groove (11) extending vertically from said thick field oxide film portion (5) through said impurity doped well region (30, 31) into said silicon substrate (1) ; selectively forming a second insulation film (12) which extends at least on vertical side walls and a bottom wall of said trench groove (11) ; selectively forming a polysilicon film (10a) on said second insulation film (12) except on its upper portion so that said polysilicon film (10a) fills with said trench groove (11) except for its upper region ; and forming an inter-layer insulator (13) which resides not only on said first insulation film (5, 16) but also on said polysilicon film (10a) so that said inter-layer insulator (13) fills up said upper region of said trench groove.

Claim 28

The method as claimed in one of the claims 21 to 24, characterized in that said first oxide film is formed by the steps of : forming a thin oxide film (16) on an entire surface of said semiconductor region (1) or of said epitaxial layer (3); and selectively forming thick field oxide films (5) so that said first insulation film (5, 16) comprises a thin silicon oxide film portion (16) and thick field oxide film portions (5) sandwiching said thin silicon oxide film portion (16) ; and characterized in that said trench groove (11) is formed which extends vertically from said thin silicon oxide film portion (16) into said semiconductor region (1) so that an opening portion of said trench groove (11) is positioned below top portions of said field oxide film portions, and an interface between said inter-layer insulator (13) and said first insulation film (5, 16) is sloped down toward said opening portion.

Claim 29

The method as claimed in one of the claims 21 to 24, characterized in that said first oxide film is formed by the steps of : forming a thin oxide film (16) on an entire surface of said semiconductor region (1) or said epitaxial layer (3); and selectively forming thick field oxide films (5) so that said first insulation film (5, 16) comprises a thick field oxide film portion (5) and thin silicon oxide film portions (16) sandwiching said thick field oxide film portion (5) ; and characterized in that said trench groove (11) is formed which extends vertically from said thick field oxide film portion (5) into said semiconductor region (1) or said silicon substrate (1).

Claim 30

The method as claimed in one of the claims 21 to 24, further comprising the step of forming spacer layers which extend both on said thin silicon oxide film portions (16) and on a part of said thick field oxide film portion (5) so that said inter-layer insulator (13) is formed which extends both on said spacer layers and on the remaining part, which is not covered by said spacer layers, of said field oxide film portion and interfaces of said inter-layer insulator (13) with said spacer layer and with said thick field oxide film portion (5) have steps which are down toward an opening of said trench groove.

Claim 31

The method as claimed in one of the claims 21 to 24, characterized in that said second isolation film is formed by the step of forming a silicon oxide film both on said first insulation film (5, 16) and on said vertical side walls and said bottom wall of said trench groove.

Claim 32

The method as claimed in one of the claims 21 to 24, characterized in that said second isolation film is formed by the steps of : forming a silicon oxide film both on said first insulation film (5, 16) and on said vertical side walls and said bottom wall of said trench groove (11) ; and forming a silicon nitride film on said silicon oxide film.

Claim 33

The method as claimed in one of the claims 21 to 26, characterized in that said inter-layer insulator (13) is formed by chemical vapor deposition of an insulation material which shows a fluidity at a high temperature.

Claim 34

The method as claimed in one of the claims 21 to 26, characterized in that said inter-layer insulator (13) is formed by chemical vapor deposition of boron phosphate silicate glass and subsequent heat treatment at a temperature of approximately 900°C for about twenty minutes.

Claim 36

The method as claimed in one of the claims 22, 24 and 26, characterized in that said polysilicon film (10a) is formed by chemical vapor deposition of polysilicon and subsequent selective etching said deposited polysilicon.