EP0720234A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Vertical power MOSFET having thick metal layer to reduce distributed resistance and method of fabricating the same
Assignee: Vishay Siliconix Inc
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Filing: 1995-12-29
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Granted: —
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Expires: 2015-12-29
Abstract
Abstract The on-resistance of a vertical power transistor is substantially reduced by forming a thick metal layer on top of the relatively thin metal layer that is conventionally used to make contact with the individual transistor cells in the device. The thick metal layer is preferably plated electrolessly on the thin metal layer through an opening that is formed in the passivation layer. <IMAGE>
Inventors
- 👤 Richard K. Williams
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 21:30
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D10/00; H10D12/00; H10D12/411; H10D12/441; H10D30/665; H10D30/668; H10D64/00; H10D64/20; H10D64/23; H10D64/251; H10D64/252; H10W; H10W20/00; H10W20/40; H10W20/482; H10W20/484; H10W72/00; H10W72/01; H10W72/019; H10W72/50; H10W72/531; H10W72/536; H10W72/5363; H10W72/541; H10W72/5438; H10W72/5453; H10W72/547; H10W72/5475; H10W72/551; H10W72/552; H10W72/5522; H10W72/5524; H10W72/59; H10W72/90; H10W72/921; H10W72/923; H10W72/926; H10W72/931; H10W72/932; H10W72/936; H10W72/951; H10W72/952
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
120 words
A vertical power transistor comprising: a die comprising a semiconductor material; a plurality of transistor cells arrayed on said die, each of said cells containing a first region located near a surface of said die and a control element and being arranged so as to permit a current to flow between said first region and a second region located at a position separated from said surface, the magnitude of said current being controlled by an electrical signal applied to said control element; a thin metal layer in electrical contact with said first region of each of said cells; and a thick metal layer deposited on said thin metal layer so as to form a low-resistance path between said first regions.
Claim 2
Dependent Claim
30 words
The power transistor of claim 1 further comprising a passivation layer over a portion of a top surface of said die, said passivation layer not covering said thick metal layer.
Claim 3
Dependent Claim
13 words
The power transistor of claim 2, wherein said passivation layer comprises silicon nitride.
Claim 4
Dependent Claim
24 words
The power transistor of claim 1,2 or 3, wherein said thick metal layer includes an adhesion sublayer in contact with said thin metal layer.
Claim 5
Dependent Claim
22 words
The power transistor of claim 4, wherein said thick metal layer includes a thick metal sublayer in contact with said adhesion layer.
Claim 6
Dependent Claim
22 words
The power transistor of claim 5, wherein said thick metal layer includes a surface sublayer in contact with said thick metal sublayer.
Claim 7
Dependent Claim
12 words
The power transistor of claim 6, wherein said surface sublayer comprises gold.
Claim 8
Dependent Claim
17 words
The power transistor of any one of claims 4 to 7, wherein said adhesion sublayer comprises zinc.
Claim 9
Dependent Claim
31 words
The power transistor of any one of claims 1 to 8, wherein said power transistor comprises a MOSFET and control element comprises a gate formed in a trench in said die.
Claim 10
Dependent Claim
12 words
The power transistor of claim 9 further comprising a gate bonding pad.
Claim 11
Dependent Claim
22 words
The power transistor of claim 10, wherein said gate bonding pad is formed of the same material as said thick metal layer.
Claim 12
Dependent Claim
23 words
The power transistor of any one of claims 1 to 11 wherein said power transistor comprises a planar vertical DMOS field effect transistor.
Claim 13
Dependent Claim
20 words
The power transistor of any one of claims 1 to 11, wherein said power transistor comprises a vertical bipolar transistor.
Claim 14
Dependent Claim
22 words
The power transistor of any one of claims 1 to 11, wherein said power transistor comprises a vertical insulated gate bipolar transistor.
Claim 15
Dependent Claim
50 words
A vertical current flow semiconductor device having a top surface comprising a passivation layer and a thick metal layer, said thick metal layer overlying a thin metal layer which is in contact with a plurality of cells of said device, a bond wire being bonded to said thick metal layer.
Claim 16
Dependent Claim
30 words
The vertical power transistor of any one of claims 1 to 14 or the device of claim 15, wherein said thick metal layer overlaps an edge of said passivation layer.
Claim 17
Dependent Claim
30 words
The vertical power transistor of any one of claims 1 to 14 or the device of claim 15, wherein said passivation layer overlaps an edge of said thin metal layer.
Claim 18
Dependent Claim
23 words
The vertical current flow semiconductor device of claim 15, wherein said thick metal layer comprises a sandwich of nickel, zinc and gold sublayers.
Claim 19
Dependent Claim
15 words
The vertical current flow semiconductor device of claim 15, wherein said bond wire comprises aluminium.
Claim 20
Dependent Claim
15 words
The vertical current flow semiconductor device of claim 15, wherein said bond wire comprises gold.
Claim 21
Independent Claim
81 words
A method of fabricating a vertical power transistor comprising the steps of: fabricating a plurality of vertical transistor cells arrayed in a semiconductor die, each of said transistor cells having a region of a selected conductivity type located as a surface of said die; depositing at least one thin metal layer over said surface, said at least one thin metal layer making electrical contact with said regions; and plating a thick metal layer over said at least one thin metal layer.
Claim 22
Independent Claim
139 words
A method of fabricating a vertical current flow device in a semiconductor die, said method comprising the steps of: forming an array of device cells in said die, each of said cells being bordered by a control element and having a semiconductor region of a selected conductivity adjacent a top surface of said die; depositing a relatively thin metal layer over said die, said relatively thin metal layer being in electrical contact with said semiconductor regions; etching an opening in said passivation layer so as to create an exposed area of said relatively thin metal layer over said device cells; and forming a relatively thick metal layer such that said thick metal layer is in electrical contact with said exposed area of said relatively thin metal layer, said relatively thick metal layer being formed at least partially by plating.
Claim 23
Dependent Claim
53 words
The method of claim 22 further comprising the step of etching said thin metal layer to form a selected pattern and wherein said step of etching an opening in said passivation layer leaves a portion of said relatively thin metal layer along a perimeter of said exposed area covered by said passivation layer.
Claim 24
Dependent Claim
33 words
The method of claim 21 or 22, wherein said relatively thick metal layer is larger in area than said opening such that a portion of said thick metal layer overlaps said passivation layer.
Claim 25
Dependent Claim
15 words
The method claim 21 or 22, wherein said relatively thick metal layer is plated electrolessly.
Claim 26
Dependent Claim
39 words
The power transistor of any one of claims 1 to 14 or the device of any one of claims 15 to 20 or the method of claims 21 to 25, wherein said relatively thick metal layer comprises primarily nickel.
Claim 27
Independent Claim
25 words
The method of claims 21 or 22, wherein the step of etching includes etching an opening in said passivation layer for a gate bonding pad.
Claim 28
Dependent Claim
29 words
The method of claim 21 or 22, wherein said step of forming said relatively thick metal layer includes depositing a metal adhesion sublayer on said relatively thin metal layer.
Claim 29
Dependent Claim
26 words
The method of claim 21 or 22, wherein said step of forming said relatively thick metal layer includes depositing a surface sublayer over a plated layer.
Claim 30
Dependent Claim
91 words
A trenched gate vertical power MOSFET comprising: a semiconductor substrate having a pattern of trenches extending into said substrate, said pattern of trenches defining a two-dimensional array of MOSFET cells; a gate disposed in said trenches, said gate being insulated from said semiconductor substrate by an insulating layer; a thin metal layer formed over said surface and extending over and making electrical contact with each of said MOSFET cells; and a thick metal layer deposited on said thin metal layer thereby to provide a low resistance path between said MOSFET cells.
Claim 31
Dependent Claim
54 words
The power MOSFET of claim 30, wherein each of said MOSFET cells comprises a source region near said surface of said substrate, a body region adjacent said source region and a drain region adjacent said body region, said thin metal layer making electrical contact with the source region in each of said MOSFET cells.
Claim 32
Dependent Claim
39 words
The power MOSFET of claim 30 or 31, wherein said body region extends to said surface in each of said MOSFET cells, said thin metal layer making electrical contact with said body region in each of said MOSFET cells.
Claim 33
Dependent Claim
22 words
The power MOSFET of claim 30 or 31, wherein said substrate comprises an epitaxial layer, said trenches extending into said epitaxial layer.
Claim 34
Dependent Claim
28 words
The power MOSFET of any one of claims 30 to 33, wherein a thickness of said thin metal layer is in the range of 0.8 to 2.8 µm.
Claim 35
Dependent Claim
28 words
The power MOSFET of any one of claims 30 to 34, wherein a thickness of said thick metal layer is in the range of 10 to 30 µm.
Claim 36
Dependent Claim
22 words
The power MOSFET of claim 30 further comprising a passivation layer, said passivation layer abutting an edge of said thick metal layer.
References Cited (Backward Citations)
No citation records indexed.
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