EP0719055A2
Expired / Lapsed
EP
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Video transmission rate matching for multimedia communication systems
Assignee: AT&T Inc
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Filing: 1995-12-06
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Granted: —
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Expires: 2015-12-06
Abstract
Abstract Improved bit rate reduction techniques are disclosed. When incorporated into an existing video processing system having a DCT coefficients processor, the motion vector processor disclosed herein provides enhanced computational and memory storage efficiencies over prior art designs. The motion vector processor includes a microprocessor and associated motion vector memory. The motion vector memory is adapted to store a plurality of motion vectors corresponding to at least one image frame containing a plurality of macro blocks. Each motion vector is represented by an X value and a Y value, the X value and the Y value signifying image changes within a given macro block from a given frame to the immediately preceding frame.
Inventors
- 👤 Li Yan
- 👤 Barin Geoffry Haskell
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 17:50
CPC Classifications
H; H04; H04N; H04N19/00; H04N19/42; H04N19/43; H04N7/00; H04N7/14; H04N7/15; H04N19/40; H04N19/50; H04N19/503; H04N19/51; H04N19/60; H04N19/61; H04N21/00; H04N21/20; H04N21/23; H04N21/234; H04N21/2343; H04N21/234354; H04N21/236; H04N21/2368; H04N21/25; H04N21/266; H04N21/2662; H04N5/00; H04N5/14; H04N5/144; H04N5/145; H04N21/60; H04N21/61; H04N21/6106; H04N21/6137
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
87 words
A motion vector processing device for use in a bit rate reduction apparatus, the processing device including: a.) processor means for performing computations on a plurality of motion vectors; each motion vector being represented by an X value and a Y value; and b.) motion vector memory means for storing a plurality of motion vectors, the plurality of motion vectors corresponding to at least one video image frame, the video image frame containing a plurality of macro blocks, each macro block being associated with a motion vector.
Claim 2
Dependent Claim
103 words
A motion vector processing device for use in a bit rate reduction apparatus having a first inverse quantizer, a second inverse quantizer, a quantizer, and a prediction frame store, the processing device including: a.) processor means for performing computations on a plurality of motion vectors; each motion vector being represented by an X value and a Y value; and b.) motion vector memory means for storing a plurality of motion vectors, the plurality of motion vectors corresponding to at least one video image frame, the video image frame containing a plurality of macro blocks, each macro block being associated with a motion vector.
Claim 3
Dependent Claim
92 words
A motion vector processing device for use in a bit rate reduction apparatus having a DCT coefficients processor, the processing device including: a.) processor means for performing computations on a plurality of motion vectors; each motion vector being represented by an X value and a Y value; and b.) motion vector memory means for storing a plurality of motion vectors, the plurality of motion vectors corresponding to at least one video image frame, the video image frame containing a plurality of macro blocks, each macro block being associated with a motion vector.
Claim 4
Dependent Claim
380 words
A bit rate reduction apparatus including: (a) a first inverse quantizer having an input and an output; (b) a second inverse quantizer having an input and an output; (c) a prediction frame store; (d) a quantizer having an input and an output; (e) processor means for performing computations on a plurality of motion vectors; each motion vector being represented by an X value and a Y value; (f) motion vector memory means for storing a plurality of motion vectors, the plurality of motion vectors corresponding to at least one video image frame, the video image frame containing a plurality of macro blocks, each macro block being associated with a motion vector; and (g) first, second, and third summing devices; each summing device having a first input, a second input, and an output; the first inverse quantizer adapted to accept an input signal in the form of quantized DCT coefficients and quantization parameters, such that an output signal of reconstructed DCT coefficients is generated; the processor means adapted to accept an input signal in the form of motion vectors; such that an output signal of processed motion vectors is generated in response to the input signal of motion vectors; the output signal being coupled to the prediction frame store; the first inverse quantizer output signal coupled to the first input of the first summing device; the prediction frame store generating an output signal in the form of a motion-compensated drift error signal; the motion-compensated drift error signal being coupled to the second input of the first summing device; the output of the first summing device being coupled to the quantizer input; the quantizer output being coupled to the second inverse quantizer input; the second inverse quantizer output being inverted and then coupled to the first input of the second summing device; the first inverse quantizer output being coupled to the second input of the second summing device; the output of the second summing device being coupled to the first input of the third summing device; the second input of the third summing device being coupled to the output signal of the prediction frame store; the output of the third summing device being coupled to the prediction frame store; the output of the quantizer comprising re-quantized DCT coefficients and new quantization parameters.
References Cited (Backward Citations)
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