MPEG2 transport decoder

Claim 2

An MPEG2 transport decoder as defined in claim 1, wherein said transport parser unit comprises: a channel decoder interface unit for inputting/outputting the data and controlling signal with said channel decoder unit; a transport decoder for storing each field value of each parsed header by parsing said MPEG2 transport packet syntax and interrupting the parsed field value to said CPU according to the condition of the interrupt register enable; a memory unit for storing program specific information(PSI) sections of the MPEG2 streams, adaptation_extension_data, transport_private_data, pes_extension_data and DSM_trick_mode_data at addresses of the memory designated by the CPU; an ADF decoder for storing each field value of each parsed header by parsing the ADF data of said MPEG2 transport packet syntaxes and interrupting the parsed field value to said CPU according to the condition of the interrupt register enable; and a PES decoder for storing each field value of each parsed header by parsing the PES section of said MPEG2 streams and interrupting the parsed field value to said CPU according to the condition of the interrupt register enable.

Claim 3

An MPEG2 transport decoder as defined in claim 2, wherein said transport decoder further comprises: a transport packet decoder controller for parsing the MPEG2 transport packet syntax; and a transport packet decoder resister for storing each header field value parsed in said transport packet decoder controller and the resisters in said transport decoder resister are accessed by said CPU.

Claim 4

An MPEG2 transport decoder as defined in claim 2, wherein said memory unit comprises: a memory for storing the PSI sections of the MPEG2 streams and the adaptation_extension_data, the transport_private_data, the PES_extension_data and the DSM_trick_mode_data contained in the selected packet, and a memory controller having start addresses and end addresses for storing each PSI data, the adaptation _extension_data, the transport_private_data, the PES_extension_data and the DSM_trick_mode_data at designated addresses in the memory and for generating write addresses with automatic change of the write address starting from the start addresses to the end addresses for storing data, whereby the memory receives data and a control signal for storing the received data from the memory controller and allows the CPU access to the received data.

Claim 5

An MPEG2 transport decoder as defined in claim 2, wherein said ADF decoder comprises: an ADF decoder controller for parsing the ADF data of said MPEG2 transport packet syntaxes; and an ADF decoder resister for storing each field value of the parsed header in said ADF decoder controller and the resisters in said ADF decoder resisters are accessed by CPU.

Claim 6

An MPEG2 transport decoder as defined in claim 2, wherein said PES decoder comprises: a PES decoder controller for parsing the PES section of said MPEG2 streams; and a PES decoder resister for storing each field value of the parsed header and the resisters in said PES decoder resisters are accessed by CPU.

Claim 7

An MPEG2 transport decoder as defined in claim 1, wherein said CPU interface unit comprises: a data buffer for performing a buffering to read/write the contents of said CPU data bus; a CPU address decoder for generating a selecting signal for selecting a resister of said transport parser unit by decoding the high address part of said CPU, a selecting signal for accessing the video, audio and another decoders and a selecting signal for accessing the program/data memory; a tp-CPU interface unit for generating a controlling signal cntrl-dsp-td for said CPU to access the resister in the transport packet decoder resister by incorporating a controlling signal of the CPU with the address signal and the selecting signal; a memory interface unit for generating a controlling signal cntrl-dsp-mem for the CPU to access the resister in the memory controller by incorporating a controlling signal of the CPU with an address signal and a selecting signal; an adf-CPU interface unit for generating a controlling signal cntrl-dsp-adf for the CPU to access the resister in the ADF decoder resister by incorporating a controlling signal of the CPU 13 with an address signal and a selecting signal; and a pes-CPU interface unit for generating a controlling signal cntrl-dsp-pes for the CPU to access the resister in the PES decoder resister by incorporating a controlling signal of the CPU with an address signal and a selecting signal.

Claim 8

An MPEG2 transport decoder as defined in claim 7, wherein said tp-CPU interface unit, memory interface unit and adf-CPU interface unit decode each address for each resister to have other address.

Claim 9

An MPEG2 transport decoder as defined in claim 1, wherein said decoder interface unit comprises: a video decoder interface unit for controlling a controlling signal for the CPU 13 and the PES decoder 24 to access the video decoder jointly; an audio decoder interface unit for controlling a controlling signal for the CPU 13 and the PES decoder 24 to access the audio decoder jointly; and a data decoder interface unit for controlling a controlling signal for the CPU 13 and the PES decoder 24 to access the data decoder jointly.

Claim 10

An MPEG2 transport decoder as defined in claim 9, wherein said video, audio and data decoder interface units comprise: a first data buffer for outputting after storing momentarily the outputted data; a memory unit for storing the data outputted from said transport parser unit and then outputting firstly the data inputted before, simultaneously with outputting the signals fifo-ef and fifo-ff indicating if the data is filled out or not; a second data buffer for outputting the data outputted from said memory unit after storing momentarily; an access controlling unit for setting the signal token giving right of an access to said CPU according to the decoder accessing condition of the CPU and the outputting signals fifo-ef and fifo-ff from said memory unit; and an interface controlling unit for controlling for said CPU to access to read/write the video decoder after finishing the present accessing job with receiving the signal token from said access controlling unit.

Claim 11

An MPEG2 transport decoder as defined in claim 9, wherein said video, audio and data decoder interface units can be partially composed in accordance with the application.

Claim 12

An MPEG2 transport decoder as defined in claims 9 and 10, wherein said video, audio and data decoder interface units are organized with sharing the memory unit.

Claim 13

An MPEG2 transport decoder as defined in claim 12, wherein said memory unit comprises: a third data buffer for storing the output data of said transport parser unit momentarily; a memory being divided into three areas of video, audio and data storing areas and storing the data inputted from said third data buffer or outputting the stored data as the decoder data; a video writing pointer for outputting a writing address in order to write the video data to said memory; an audio writing pointer for outputting a writing address in order to write the audio data to said memory; a data writing pointer for outputting a writing address in order to write the data to said memory; a first address buffer for storing momentarily the address outputted from said video writing pointer; a second address buffer for storing momentarily the address outputted from said audio writing pointer; a third address buffer for storing momentarily the address outputted from said data writing pointer; a video reading pointer for outputting a reading address in order to read the video data to said memory; an audio reading pointer for outputting a reading address in order to read the audio data to said memory; a data reading pointer for outputting a reading address in order to read the data to said memory; a fourth address buffer for storing momentarily the address outputted from said video reading pointer; a fifth address buffer for storing momentarily the address outputted from said audio reading pointer; a sixth address buffer for storing momentarily the address outputted from said data reading pointer; and a memory interface controller for controlling the operations of said vide, audio and data reading/writing pointers and said first to sixth address buffers by the controlling signal cntrl5 from the PES decoder.