Video decoder capable of controlling encoded video data rate

Claim 2

The video decoding apparatus according to Claim 1, wherein said video bit stream control circuit(3,5,6,7) changes said threshold value(Bthn) in proportion to a playback speed for said decoded pictures.

Claim 3

The video decoding apparatus according to Claim 2, wherein said video bit stream control circuit(3,5,6,7) operates to skip a portion of said video bit stream in the unit of picture, as long as the amount of data stored in said bit buffer(2) exceeds said threshold value(Bthn).

Claim 4

The video decoding apparatus according to Claim 2, wherein said video bit stream control circuit(3,5,6,7) changes said threshold value based upon a video buffering verifier (VBV) buffer size, a bit rate and a picture rate which are defined by a sequence header included in said video bit stream, and based upon a magnification of an actual playback speed for a normal playback speed.

Claim 5

A video decoding apparatus for decoding a coded video bit stream including a series of pictures including an I-picture, a P-picture and a B-picture to produce decoded pictures, comprising: a bit buffer(2) for temporarily storing said video bit stream; a decoding circuit(4) for receiving said video bit stream output from said bit buffer(2) and decoding said video bit stream to produce decoded pictures, characterized by further comprising: a video bit stream control circuit(3,5,6,7), operatively connected to said bit buffer(2) and said decoding circuit(4), for controlling an amount of said video bit stream to be supplied to said decoding circuit(4) from said bit buffer(2) based on an amount of data of said video bit stream stored in said bit buffer(2), wherein said control circuit(3,5,6,7) includes: means(5) for determining whether an amount of data stored in said bit buffer(2) exceeds a first threshold value(B3thn) that is predetermined as an amount of said video bit stream which can be safely stored in said bit buffer(2), said determining means(5) further operates to change said first threshold value(B3thn) in proportion to a playback speed of said decoded pictures, and wherein said control circuit(3,5,6,7) operates to allow said video bit stream of said I-picture and said P-picture to be supplied to said decoding circuit(4), and operates to skip said video bit stream of said B-picture in order to prevent said video bit stream of said B-picture from being supplied to said decoding circuit(4) from said bit buffer(2) as long as the amount of data stored in said bit buffer(2) exceeds said first threshold value(B3thn).

Claim 6

The video decoding apparatus according to Claim 5, wherein said video bit stream control circuit(3,5,6,7) skips said video bit stream of said B-picture to be supplied next, even when an amount of data of said video bit stream stored in said bit buffer(2) is smaller than said first threshold value(B3thn), after said video bit stream of said I-picture or said P-picture is supplied to said decoding circuit(4) from said bit buffer(2).

Claim 7

The video decoding apparatus according to Claim 5, wherein said determining means(5) determines whether the amount of data stored in said bit buffer(2) exceeds the first threshold value(B3thn) and a second threshold value(B2thn) higher than the first threshold value(B3thn), and wherein said video bit stream control circuit(3,5,6,7) skips said video bit stream of said B-picture when the amount of data stored in said bit buffer(2) exceeds said first threshold value(B3thn), after said video bit stream of said I-picture or said P-picture is supplied to said decoding circuit(5), and skips said video bit stream of said B-picture when the amount of data stored in said bit buffer(2) exceeds said second threshold value(B2thn), after said video bit stream of said P-picture is supplied to said decoding circuit(5).

Claim 8

The video decoding apparatus according to Claim 7, wherein said video bit stream control circuit(3,5,6,7) changes said first and second threshold values(B3thn,B2thn) based upon a video buffering verifier (VBV) buffer size, a bit rate and a picture rate which are defined by a sequence header included in said video bit stream, and based upon a magnification of an actual playback speed for a normal playback speed.

Claim 9

A video decoding apparatus for decoding a coded video bit stream including a series of pictures including an I-picture, a P-picture and a B-picture to produce decoded pictures, comprising: a video bit stream analyzer(12) for determining a type of each picture included in said video bit stream and analyzing an amount of data of said video bit stream picture by picture; a bit buffer(2) for temporarily storing said video bit stream from said video bit stream analyzer(12); a decoding circuit(4) for receiving said video bit stream output from said bit buffer(2) and decoding said video bit stream to produce decoded pictures; and a video bit stream control circuit(3,5,6,7), operatively connected to said bit buffer(2) and said decoding circuit(4), for controlling an amount of said video bit stream to be supplied to said decoding circuit(4) from said bit buffer(2) based upon an amount of data of said video bit stream stored in said bit buffer(2), wherein said control circuit(3,5,6,7) includes: means(5) for determining whether an amount of data stored in said bit buffer(2) exceeds a threshold value that is predetermined as an amount of said video bit stream which can be safely stored in said bit buffer(2), said determining means(5) further operates to change said threshold value in proportion to a playback speed of said decoded pictures, and wherein, when said determining means(5) determines that the amount of data stored in said bit buffer(2) exceeds the threshold value, said control circuit(3,5,6,7) operates to selectively skip a portion of said video bit stream in the unit of a picture in order to prevent said video bit stream from being supplied to said decoding circuit(4) from said bit buffer(2), and the portion to be skipped is selected based upon the type of each picture and the amount of data for each picture, detected by said video bit stream analyzer(12).

Claim 10

The video decoding apparatus according to Claim 9, further comprising a frame buffer(22) for storing decoded pictures produced by said decoding circuit, said frame buffer (22)including: a forward reference area(22a) for storing a decoded I-picture or P-picture to be used in backward prediction decoding to be executed by said decoding circuit(4); a backward reference area(22b) for storing a decoded I-picture or P-picture to be used in forward prediction decoding to be executed by said decoding circuit(4); and a B-picture storage area(22c) for storing a decoded B-picture, wherein said video bit stream control circuit(3,5,6,7) uses said B-picture storage area(22c) as an expansion memory for said bit buffer(2) when skipping said B-pictures within said video stream.

Claim 11

The video decoding apparatus according to Claim 9, wherein said decoding circuit(4) continuously produces two decoded I-pictures or P-pictures in one frame period, stores the first I-picture or P-picture as a reference picture in forward prediction decoding or backward prediction decoding, and outputs the second I-picture or P-picture, which has been decoded later, as a playback picture.

Claim 12

The video decoding apparatus according to Claim 10, wherein said decoding circuit(4) continuously produces two decoded I-pictures or P-pictures in one frame period, stores the first I-picture or P-picture as a reference picture in forward prediction decoding or backward prediction decoding to said B-picture storage area(22c), and outputs the second I-picture or P-picture, which has been decoded later, as a playback picture.

Claim 13

The video decoding apparatus according to Claim 9, wherein said video bit stream control circuit(3,5,6,7) changes said threshold values based upon a video buffering verifier (VBV) buffer size, a bit rate and a picture rate which are defined by a sequence header included in said video bit stream, and based upon a magnification of an actual playback speed for a normal playback speed.

Claim 14

A video decoding apparatus for decoding a coded video bit stream including a series of pictures including an I-picture, a P-picture and a B-picture to produce decoded pictures, comprising: a bit buffer(33) for temporarily storing said video bit stream, said bit buffer(33) having a capacity defined by adding a value(X) obtained by dividing a bit rate by a picture rate to a video buffering verifier (VBV) buffer size(B); a decoding circuit(4) for receiving said video bit stream output from said bit buffer(33) and decoding said video bit stream to produce decoded pictures, characterized by further comprising: a video bit stream control circuit(3,6,7,34), operatively connected to said bit buffer(33) and said decoding circuit(4), for controlling an amount of said video bit stream to be supplied to said decoding circuit(4) from said bit buffer(33) based on an amount of data of said video bit stream stored in said bit buffer(33), wherein said control circuit(3,6,7,34) includes: means(34) for determining whether an amount of data stored in said bit buffer(33) exceeds a first threshold value(BTH1) indicative of said VBV buffer size(B) and a second threshold value(BTH2) indicative of a value obtained by adding a value(X) resulting from division of said bit rate by said picture rate to said VBV buffer size(B), wherein said control circuits(3,6,7,34) operates to allow said video bit streams of said I-picture and said P-picture to be supplied to said decoding circuit(4), and operates to skip said video bit stream of said B-picture in order to prevent said video bit stream of said B-picture from being supplied to said decoding circuit(4) from said bit buffer(33) as long as the amount of data of stored in said bit buffer (33) lies between said first threshold value(BTH1) and said second threshold value(BTH2), and further operates to skip a portion of said video bit stream regardless of a type of a picture as long as said amount of data stored in said bit buffer(33) exceeds said second threshold value(BTH2).

Claim 15

The video decoding apparatus according to Claim 14, wherein said video bit stream control circuit(3,6,7,34) includes: a picture header detector(3) for determining a type of a picture based on a picture header included in said video bit stream output from said bit buffer(33).

Claim 16

The video decoding apparatus according to Claim 14, wherein said bit buffer(33) has a capacity defined by adding a value(X), obtained by dividing said bit rate by said picture rate, and a margin value to said VBV buffer size(B).

Claim 17

A video decoding apparatus for decoding a coded video bit stream including a series of pictures to produce decoded pictures, comprising: a bit buffer(2) for temporarily storing said video bit stream; a decoding circuit(4) for receiving said video bit stream output from said bit buffer(2) and decoding said video bit stream to produce decoded pictures, characterized by further comprising: an operation control circuit(3,7,42) for controlling a reading operation of said bit buffer(2) and a decoding operation of said decoding circuit(4) based on an amount of data of said video bit stream stored in said bit buffer(2), wherein said operation control circuit(3,7,42) operates to inhibit said reading operation of said bit buffer(2) and said decoding operation of said decoding circuit(4) in order to supply already decoded pictures during a period from a point of time at which an underflow of said bit buffer(2) has occurred to a point of time at which the underflow is released.

Claim 18

The video decoding apparatus according to Claim 17, wherein said operation control circuit(3,7,42) includes means(42) for determining whether an amount of data stored in said bit buffer(2) exceeds a threshold value that is predetermined as an amount of said video bit stream and indicates a possibility of an underflow of said bit buffer(2), and said operation control circuit(4) inhibits said reading operation of said bit buffer(2) and said decoding operation of said decoding circuit(4) in order to supply already decoded pictures, so long as the amount of data stored in said bit buffer(2) is smaller than said threshold value.

Claim 19

The video decoding apparatus according to Claim 18, wherein said threshold value is set to a value obtained by multiplying said bit rate by a video buffering verifier (VBV) delay value.

Claim 20

The video decoding apparatus according to Claim 17, wherein said pictures include an I-picture, a P-picture and a B-picture, said operation control circuit(3,7,42) determines a type of a picture based on a picture header included in said video bit stream output from said bit buffer(2), and, when said underflow of said bit buffer(2) has occurred during decoding of said B-picture, said operation control circuit(3,42,7) skips a remaining portion of said video bit stream of B-picture and continues decoding.

Claim 21

The video decoding apparatus according to Claim 17, wherein said pictures include an I-picture, a P-picture and a B-picture, said operation control circuit(3,7,42) determines a type of a picture based on a picture header included in said video bit stream output from said bit buffer(2), and, when said underflow of said bit buffer(2) has occurred during decoding of said I-picture or said P-picture, said operation control circuit(3,7,42) interrupts said decoding, and continues decoding said video bit stream of said I-picture or P-picture after releasing of said underflow.

Claim 22

The video decoding apparatus according to Claim 21, further comprising a frame buffer(22) for storing decoded pictures produced by said decoding circuit(4), said frame buffer(22) including: a forward reference area(22a) for storing a decoded I-picture or P-picture to be used in backward prediction decoding to be executed by said decoding circuit(4); a backward reference area(22b) for storing a decoded I-picture or P-picture to be used in forward prediction decoding to be executed by said decoding circuit(4); and a B-picture storage area(22c) for storing a decoded B-picture.

Claim 23

The video decoding apparatus according to Claim 22, wherein said operation control circuit(3,7,42) controls said frame buffer(22) in such a manner that when a decoded first I-picture or P-picture has been transferred to said forward reference area(22a), a second decoded I-picture or P-picture already stored in said-backward reference area(22b) or the decoded B-picture stored in said B-picture storage area(22c) is read as a playback picture, and that when a decoded third I-picture or P-picture has been transferred to said backward reference area(22b), a fourth decoded I-picture or P-picture already stored in said forward reference area(22a) or the decoded B-picture stored in said B-picture storage area(22c) is read as said playback picture.