An integrated circuit that performs multiple communication tasks

Claim 2

The integrated circuit (24) of claim 1, wherein the central processing unit (58) is coupled to the memory (70) and the first co-processor (72) via an address bus (52), a control bus (54), and a data bus (50).

Claim 3

The integrated circuit (24) of claim 2, wherein the central processing unit (58) controls execution of the echo cancellation algorithm (96) by the first co-processor (72) by providing control signals to the first co-processor (72) via the control bus (54).

Claim 4

The integrated circuit of claim 1 further comprises a third co-processor (64) operably coupled to the memory (70) and the central processing unit (58), wherein the third co-processor (64) executes, under control of the central processing unit (58), a second portion of the modem processing algorithm (92).

Claim 5

An integrated circuit (24) comprising: memory (70) that stores an audio coding algorithm (88), a modem processing algorithm (92), audio data (86), and transmit data (118); signal converter (56) operably coupled to the memory (70), wherein the signal converter 956) provides an analog-to-digital input port (78) and wherein the analog-to-digital input port (78) provides audio data (86) to the memory (70); a central processing unit (58) operably coupled to the memory (70), wherein the central processing unit (58) executes at least a first portion of the audio coding algorithm (88) and at least a first portion of the modem processing algorithm (92) upon the audio data (86) to produce the transmit data (118); a modulation signal converter (68) operably coupled to the memory (70), wherein the modulation signal converter (68) receives first band analog data (82) and converts the first band analog data to first digital data (120), and receives second digital data (122) and converts the second digital data (122) to a second band analog output (84); and a digital modulator (110) operably coupled to the modulation signal converter (68) and the memory (70), wherein the digital modulator (110) produces the second digital data (122) based on the transmit data (118) and provides the second digital data (122) to the modulation signal converter (68).

Claim 6

The integrated circuit (24) of claim 5, wherein the central processing unit (58) further executes at least a first portion of an audio decoding algorithm (116) upon the first digital data (120) to produce digital audio information (112).

Claim 7

An integrated circuit (24) comprising: modulation signal converter (68) that receives first band analog data (82) and converts the first band data (82) to first digital data (120), and converts second digital data (122) to second band data (84); equalizer (124) operably coupled to the modulation signal converter (68), wherein the equalizer (124) converts the first digital data (120) into an equalized data stream (126); channel decoder (130) operably coupled to the equalizer (124), wherein the channel decoder (130) converts the equalized data stream (124) into decoded audio information (132); first audio processor (134) operably coupled to the channel decoder (130), wherein the first audio processor (134) converts the decoded audio information (132)into first digitized audio data (136); signal converter (56) operably coupled to the first audio processor (134), wherein the signal converter (56) converts the first digitized audio data (136) into an analog audio signal (26), and wherein the signal converter (56) converts an input analog signal (28) into second digitized audio data (138); second audio processor (140) operably coupled to the signal converter (56), wherein the second audio processor (140) converts the second digitized audio data (138) into processed audio information (142); channel encoder (144) operably coupled to the second audio processor (140), wherein the channel encoder (144) converts the processed audio information (142) into encoded data stream (146); and digital signal modulator (110) operably coupled to the channel encoder (144) and the modulation signal converter (68), wherein the digital signal modulator (110) converts the encoded data stream (146) into the second digital data (122).

Claim 8

The integrated circuit (24) of claim 7 further comprises a command parser (162) that provides an auxiliary audio/data command signal (166) to the channel encoder (144) and the channel decoder (130), wherein the auxiliary audio/data command signal (166) indicates whether the integrated circuit (24) is processing auxiliary input data, auxiliary output data, auxiliary input audio, or auxiliary output audio.

Claim 10

The method of claim 9 further comprises receiving an auxiliary audio/data command (166), wherein the auxiliary audio/data command (166) indicates whether the integrated circuit (24) is processing auxiliary input data (157), auxiliary output data (158), auxiliary input audio (155), or auxiliary output audio (158).