EP0710981A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Improvements in or relating to electronic devices
Assignee: Texas Instruments Inc
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Filing: 1995-11-02
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Granted: —
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Expires: 2015-11-02
Abstract
Abstract A semiconductor device and process for making the same are disclosed which use embedded pillars to prevent damage (e.g. dishing, smearing, overetching) to damascene conductors, particularly large conductors. For example, a channel may be formed in an insulating layer such that one or more insulating pillars within the channel are left intact during channel etching. A conductive film may be deposited over the insulating layer, preferably largely comprised of low-resistivity, relatively soft materials such as Al, Cu, or Al-Cu alloys. Chemical-mechanical polishing is then used to remove portions of the conductive film overlying non-channeled areas of the insulating layer to form an inlaid conductor. It has been found that wide conductors or pads may experience much more damage than narrow conductors during polishing. Pillars may therefore be used in a wide conductor to control polish damage to such a conductor.
Inventors
- 👤 Manoj Kumar Jain
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 14:01
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/063; H10W20/062; G; G06; G06F; G06F2119/00; G06F2119/18; Y; Y02; Y02P; Y02P90/00; Y02P90/02
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
117 words
A method of forming a semiconductor device having an inlaid conductor, wherein said semiconductor device has an insulating layer deposited on a substrate, said insulating layer having a substantially planar upper surface, said method comprising: removing at least a top portion of said insulating layer in a predefined area on said device, thereby forming a channel in the upper surface; forming at least one pillar within said channel, said pillar having a top surface substantially coplanar with the upper surface of the insulating layer; depositing a conductive film over said insulating layer such that the top surface of said conductive film is substantially coplanar with said upper surface of said insulating layer, thereby creating the inlaid conductor;
Claim 2
Dependent Claim
42 words
The method of claim 1, further comprising polishing said device such that the surface of the conductive film is rendered substantially plainar and such that the pillar acts as a stop to prevent damage to said inlaid conductor during said polishing step.
Claim 3
Dependent Claim
23 words
The method of claim 1 or claim 2, further comprising forming said insulating layer of two or more adjacent sublayers differing in composition.
Claim 4
Dependent Claim
26 words
The method of claim 3, further comprising selecting the material of the sublayers are from the group consisting of silicon dioxide, silicon nitride, or combinations thereof.
Claim 5
Dependent Claim
29 words
The method of claim 3 or claim 4, further comprisingly etching the topmost of said sublayers from said predefined area to form at least a portion of said channel.
Claim 6
Dependent Claim
13 words
The method of claim 5, further comprising etching vias in said insulating layer.
Claim 7
Independent Claim
22 words
The method of any preceding claim, further comprising carrying out the removing and forming steps simultaneously, such that said pillar is integral.
Claim 8
Independent Claim
43 words
The method of any preceding claim, wherein said forming at least one pillar step comprises the steps of depositing a pillar film over said insulating layer and said channel, and patterning and etching said pillar film, thereby forming said pillar within said channel.
Claim 9
Independent Claim
22 words
The method of any preceding claim, further comprising forming the conducting film comprised of two or more adjacent sublayers, differing in composition.
Claim 10
Dependent Claim
26 words
The method of claim 9, further comprising selecting sublayers from the group of materials consisting of: Ti, TiN, TiW, W, Al, Cu, Pd, or combinations thereof.
Claim 11
Dependent Claim
18 words
The method of claim 9 or claim 10, further comprising conformally depositing at least one of said sublayers.
Claim 12
Independent Claim
23 words
The method of any preceding claim, wherein said polishing step comprises chemical-mechanical polishing with a slurry providing both abrasive and chemically reactive components.
Claim 13
Independent Claim
13 words
The method of any preceding claim, further comprising forming a damascene interconnection layer.
Claim 14
Dependent Claim
89 words
A semiconductor device having a damascene metallization structure thereon, said structure comprising: an insulating layer formed on a substrate, said insulating layer having a substantially planar upper surface with a plurality of channels formed therein; and conductors inlaid in said channels such that the top surface of said conductors is substantially coplanar with said insulating layer upper surface, at least one of said conductors comprising a set of contiguous conducting segments inlaid such as to surround at least one pillar extending substantially to the level of said upper surface.
Claim 15
Dependent Claim
14 words
The structure of claim 14, wherein said pillar is formed of an insulative material.
Claim 16
Dependent Claim
22 words
The structure of claim 14 or claim 15, further comprising a second insulating layer over said first insulating layer and said conductors.
Claim 17
Dependent Claim
22 words
The structure of claim 16, further comprising a metallization layer electrically connected through said second insulating layer to said damascene metallization structure.
References Cited (Backward Citations)
US4944836A
Cited
US5262354A
Cited
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