DC-DC converter functioning in pulse skipping mode under low load conditions

Claim 2

A method as defined in claim 1, wherein said inhibiting is implemented by masking the switching to a logic "0" of a high frequency timing signal of the converter for the entire period of time said current remains below said minimum threshold value.

Claim 3

A DC-to-DC static converter composed of a power section which comprises at least a switch driven at a switching frequency set by a clock or local oscillator signal, an inductor, a discharge diode, an output storage capacitor, a PWM control loop suitable to control the duty-cycle of said switch by commanding the turning off in function of the current level in the inductor and of the output voltage of the converter, and a control circuit for reducing the overall switching frequency during idle periods as long as the current in the inductor remains below a minimum threshold value set by a comparator, characterized by comprising logic means capable of inhibiting any turn-off command of said PWM control loop switch of the converter for as long as the current in the inductor remains below said minimum threshold value.

Claim 4

A converter as defined in claim 3, wherein said logic means mask the transition to "0" of said clock or local oscillator signal.

Claim 5

A static DC-to-DC converter composed of a power section which comprises at least a switch switching at a frequency set by a clock or local oscillator timing signal, an inductor, a discharge diode and an output storage capacitor charged by the discharge current of said inductor, a PWM control loop comprising an error amplifier and a comparator for controlling the duty-cycle of said switch in function of the current in the inductor as detected by a sensing resistance and the output voltage on said storage capacitor, a flip-flop driving said switch and having a "set" input to receive said timing signal and a reset input for receiving a control signal produced by said PWM control loop, at least a second comparator, the inputs of which are functionally connected to said sensing resistance, characterized by comprising a first OR logic circuit having a first input connected to the output of said second comparator, a second input to which a drive signal of said switch is applied and an output; a second AND logic circuit having a first input connected to the output of said first OR logic circuit, a second input connected to an output of said PWM control loop and an output connected to said reset input of said driving flip-flop; a third NAND logic circuit having a first input connected to the output of said first OR logic circuit, a second input connected to said set input of said flip-flop and an output; a fourth NAND logic circuit having an input connected to an output of said flip-flop, a second input connected to the output of said third NAND logic circuit and an output connected to a control terminal of said switch.