BiCDMOS process technology and structures

Claim 1

Method for forming an MOS transistor in conjunction with transistors of a different type in the same substrate comprising the steps of: forming a gate (351) of said MOS transistor overlying and isolated (357) from a channel region (360) of a semiconductor material (42) of a first conductivity type; forming a source region (352) of a second conductivity type; adjusting a threshold voltage of said MOS transistor by implanting dopants of said second conductivity type into said channel region in said semiconductor material at an implant energy such that said dopants of said second conductivity type penetrate said gate to implant into said channel region, said dopants being sufficient to change a threshold voltage of said MOS transistor to achieve a desired threshold, said step of adjusting a threshold voltage of said MOS transistor occurring after a diffusion step for forming a diffused body (308) or base region (310) of another transistor in said same substrate to prevent said dopants of said second conductivity in said channel region from being subjected to said diffusion step.

Claim 5

The method of any of Claims 1, 2, 3, or 4 wherein said source is formed after said step of adjusting said threshold voltage.

Claim 6

The method of any of Claims 1, 2, 3, or 4 wherein said source region (352) is formed before said step of adjusting said threshold voltage.

Claim 7

The method of any of Claims 1 through 6 wherein said step of adjusting said threshold voltage of said MOS transistor is conducted without any additional masking steps over that used to form said source region (352).

Claim 8

The method of any of Claims 1 through 6 wherein said step of adjusting said threshold voltage of said MOS transistor is conducted without any additional masking steps over that used to form said source region (352), and said step of adjusting said threshold voltage also implants dopants of said seocnd conductivity type into other exposed N or P conductivity regions on said semiconductor material.

Claim 9

The method of any of Claims 2 through a wherein said second dosage is on the order of 1OE12 ions per cm².

Claim 10

The method of any of Claims 1 through 9 wherein said step of forming said source region (352) comprises patterning a photoresist masking layer (360) overlying said semiconductor material (42) and depositing dopants of said second conductivity type into exposed portions of said semiconductor material to form said source region self-aligned with said gate (351), and wherein said step of adjusting said threshold voltage is conducted while said photoresist masking layer remains overlying said semiconductor material so that said step of adjusting said threshold voltage does not entail another masking step.

Claim 12

A method for forming a lateral MOS transistor having a lightly doped drain (154) for increased breakdown voltage and for forming other transistors in the same substrate, said method comprising the steps of: forming a first gate (110E) for a lateral MOS transistor and a second gate (11OA) for a DMOS transistor overlying and insulated from a semiconductor material (42); forming a masking layer (120) over said semiconductor material to mask a first area around said first gate and expose a second area (121A) around said second gate; implanting ions of a first conductivity type into said second area using said second gate and said masking layer as a mask for forming a self-aligned body region (122) of said first conductivity type for said DMOS transistor; removing said masking layer to expose said first area around said first gate and expose said second area around said second gate; implanting ions of a second conductivity type into said first area and said second area, said first gate and said second gate acting as a mask to self-align implantation of said ions of said second conductivity type with said first gate and said second gate, said ions of said second conductivity type counter-doping said body region of said DMOS transistor and forming a lightly doped drain (154) of said lateral transistor self-aligned with said second gate, said step of implanting said ions of said first conductivity type being adjusted to take into account said counter-doping from said implantation of said ions of said second conductivity type into said body region so that said body region has desired electrical characteristics; and implanting ions of said second conductivity type into said body region to form a source region (152) of said DMOS transistor and into said lightly doped drain region to form a drain region (155) of said lateral MOS transistor.