EP0707426A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Digital video decoder for decoding digital high definition and/or digital standard definition television signals
Assignee: Hitachi Ltd
•
Filing: 1995-10-10
•
Granted: —
•
Expires: 2015-10-10
Abstract
Abstract Methods and apparatus for reducing the complexity of decoder circuitry and video decoder memory requirements are disclosed. The discribed video decoders are capable of decoding HDTV and/or SDTV pictures. The described video decoder may be used as part of a picture-in-picture decoder circuit for providing picture-in-picture capability without providing multiple full resolution video decoders. The reduction in decoder circuit complexity is achieved through the use of a plurality of data reduction techniques including the use of a preparser, downsampling, and truncating pixel values.
Inventors
- 👤 Jill Macdonald Boyce
- 👤 Larry Pearlstein
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 14:50
CPC Classifications
H; H04; H04N; H04N19/00; G; G06; G06T; G06T3/00; G06T3/40; G06T3/4007; G06T3/4084; G11; G11B; G11B5/00; G11B5/008; G11B5/00813; G11B5/00847; G11B5/0086; H03; H03M; H03M7/00; H04N19/10; H04N19/102; H04N19/117; H04N19/124; H04N19/132; H04N19/134; H04N19/136; H04N19/137; H04N19/139; H04N19/157; H04N19/159; H04N19/16; H04N19/162; H04N19/169; H04N19/17; H04N19/172; H04N19/176; H04N19/18; H04N19/184; H04N19/189; H04N19/192; H04N19/40; H04N19/42; H04N19/423; H04N19/426; H04N19/427; H04N19/428; H04N19/44; H04N19/46; H04N19/48; H04N19/50; H04N19/503; H04N19/51; H04N19/513; H04N19/587; H04N19/59; H04N19/60; H04N19/61; H04N19/70; H04N19/80; H04N19/82; H04N19/90; H04N21/00; H04N21/20; H04N21/23; H04N21/231; H04N21/23106; H04N21/234; H04N21/2343; H04N21/236; H04N21/25; H04N21/266; H04N21/2662; H04N21/40; H04N21/41; H04N21/426; H04N21/43; H04N21/431; H04N21/4312; H04N21/4316; H04N21/432; H04N21/4325; H04N21/434; H04N21/438; H04N21/4382; H04N21/44; H04N21/4402; H04N21/440254; H04N21/440263; H04N21/45; H04N21/462; H04N21/4621; H04N5/00; H04N5/44; H04N5/445; H04N5/45; H04N5/46; H04N9/00; H04N9/79; H04N9/80; H04N9/804; H04N9/8042; G11B15/00; G11B15/02; G11B15/12; G11B15/125; G11B15/18; G11B15/1808; G11B15/1875; G11B15/46; G11B15/467; G11B15/4673; H04N19/13; H04N19/30; H04N19/91; H04N5/76; H04N5/78; H04N5/782; H04N5/7824; H04N5/7826; H04N5/78263; H04N9/82; H04N9/8205; H04N9/8227
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
87 words
A decoder circuit for decoding digital video data including pictures at a resolution less than the full resolution of the pictures, each picture including a plurality of macroblocks, each macroblock including a plurality of DCT coefficients, the decoder circuit comprising: preparser means for receiving the digital video data and for removing from each macroblock DCT coefficients that exceed a preselected maximum number of DCT coefficients per macroblock; and a channel buffer coupled to the preparser means for temporarily storing the video data output by the preparser means.
Claim 2
Dependent Claim
70 words
The decoder of claim 1, wherein each DCT coefficient is represented by a number of bits and wherein each macroblock is represented by the total number of bits representing the DCT coefficients included in the macroblock, and wherein the preparser means operates to remove DCT coefficients from each individual macroblock until the number of bits used to represent the individual macroblock does not exceed a predetermined maximum number of bits.
Claim 3
Dependent Claim
49 words
The decoder of claim 1, wherein the channel buffer is further coupled to the preparser by a feedback line and wherein the channel buffer signals the preparser to control the output data rate of the preparser as a function of the amount of data stored in the channel buffer.
Claim 4
Dependent Claim
86 words
The decoder of claim 1, further comprising a syntax parser and variable length decoder circuit coupled to the channel buffer; and an inverse quantization circuit coupled to the syntax parser and variable length decoder circuit for inverse quantizing only a limited preselected number of DCT coefficients per macroblock and for outputting zeros corresponding to the DCT coefficients of the macroblock which are not inverse quantized, wherein the limited number of DCT coefficients per macroblock is less than a maximum possible number of DCT coefficients per macroblock.
Claim 5
Dependent Claim
33 words
The decoder circuit of claim 4, wherein the limited preselected number of DCT coefficients per macroblock is less than 11 and wherein the maximum possible number of DCT coefficients per macroblock is 64.
Claim 6
Dependent Claim
34 words
The decoder circuit of claim 4, further comprising an inverse DCT circuit coupled to the inverse quantizer circuit for performing an inverse DCT operation on the limited preselected number of DCT coefficients per macroblock.
Claim 7
Dependent Claim
65 words
The decoder circuit of claim 1, further comprising: a syntax parser and variable length decoder circuit coupled to the channel buffer; a downsampler coupled to the syntax parser and variable length decoder circuit for downsampling the video pictures output by the syntax parser to thereby reduce the amount of resolution of each picture and the amount of video data used to represent each video picture.
Claim 8
Dependent Claim
126 words
The decoder circuit of claim 7, wherein the pictures further include motion vectors, and wherein the decoder circuit further comprises: a frame buffer coupled to the downsampler for storing the reduced resolution pictures generated by the downsampler; and a motion compensation circuit coupled to the frame buffer, the motion compensation circuit including: i. an upsampler circuit for upsampling the reduced resolution pictures to generate prediction reference pictures; ii. an interpolation circuit for interpolating the predication reference pictures; iii. a motion compensated prediction module for applying the motion vectors to the prediction reference pictures to generate new pictures; and iv. a downsampler circuit coupled to the motion compensated prediction module for downsampling the new pictures to the same resolution as the pictures stored in the frame buffer.
Claim 9
Independent Claim
103 words
A method of decoding variable length encoded digital video data including pictures, to a resolution less than the full resolution of the pictures, each picture including a plurality of macroblocks, each macroblock including a plurality of DCT coefficients, the method comprising the steps of: receiving digital video data; parsing the digital video data to identify macroblocks included in the digital video data and the DCT coefficients included in the identified macroblocks; discarding from the digital video data the DCT coefficients included in each macroblock that exceed a preselected number of DCT coefficients; and storing the digital video data in a coded data buffer.
Claim 10
Dependent Claim
85 words
The decoding method of claim 9, wherein each DCT coefficient is represented by a number of bits and wherein each macroblock is represented by the total number of bits representing the DCT coefficients included in the macroblock, the method further comprising the step of: prior to storing the digital video data in a coded data buffer, discarding DCT coefficients from each identified macroblock until each identified macroblock is represented by a total number of bits that is less than a preselected maximum number of bits.
Claim 11
Dependent Claim
63 words
The method of claim 10, further comprising the steps of: monitoring the amount of data stored in the coded data buffer to determine coded data buffer occupancy; and dynamicly adjusting the total number of bits allowed per macroblock from the preselected maximum number to a smaller number as coded data buffer occupancy increases to insure that the coded data buffer does not overflow.
Claim 12
Dependent Claim
79 words
The method of claim 9, further comprising the steps of: syntax parsing and variable length decoding the video data stored in the coded data buffer to generate a variable length decoded video data stream including macroblocks, each macroblock including a plurality of DCT coefficients; and inverse quantizing a preselected number of DCT coefficients included in each macroblock of the variable length decoded video stream and outputting zero values corresponding to the macroblock DCT coefficients which are not inverse quantized.
Claim 13
Dependent Claim
23 words
The method of claim 12, further comprising the step of: performing an inverse discrete cosine transform operation on the inverse quantized video data.
Claim 14
Dependent Claim
48 words
The method of claim 13, further comprising the steps of: downsampling the video data to reduce the resolution of the inverse quantized video data and to reduce the amount of memory required to store the inverse quantized video data; and storing the video data in a frame buffer.
Claim 15
Dependent Claim
46 words
The method of claim 14, further comprising the steps of: upsampling the video data stored in the frame buffer; interpolating the upsampled video data; performing motion compensated prediction on the upsampled video data; and downsampling the upsampled video data upon which motion compensated prediction was performed.
Claim 16
Dependent Claim
33 words
The method of claim 15, wherein the downsampling operation performed on the video data after performing motion compensated prediction is an exact inverse of the upsampling performed prior to performing motion compensated prediction.
Claim 17
Independent Claim
76 words
A method of decoding digital data representing a video frame, the digital data representing each video frame including video data representing a plurality of pixels, the video data representing each pixel including a set of bits, the method comprising the step of: truncating the least significant bit from each set of bits representing one of the individual pixels; and storing the truncated set of bits representing each one of the individual pixels in a frame buffer.
Claim 18
Dependent Claim
41 words
The method of claim 17, further comprising the steps of: reading data out of the frame buffer; and appending a zero to each set of bits representing one of the individual pixels as it is read out of the frame buffer.
Claim 19
Dependent Claim
21 words
The method of claim 18, further comprising the step of: low pass filtering the data read out of the frame buffer.
Claim 20
Dependent Claim
144 words
A digital picture-in-picture decoder circuit for decoding a primary picture to be displayed in a primary picture area and a second picture to be displayed in a secondary picture area, the secondary picture area being smaller than the primary picture area, the decoder circuit comprising: a full resolution video decoder for receiving and decoding a first set of digital video data including the primary picture; a first reduced resolution video decoder for receiving a second set of digital video data including the second picture and for decoding the received video data to generate a reduced resolution version of the second picture; and a post processor circuit coupled to the full resolution decoder circuit and the reduced resolution decoder circuit, the post processor circuit operating to combine the primary full resolution picture and the reduced resolution version of the second picture into a single picture.
Claim 21
Dependent Claim
45 words
The digital picture-in-picture decoder circuit of claim 20, wherein the full resolution video decoder is a HDTV decoder and wherein the reduced resolution video decoder is a reduced resolution video decoder that generates pictures 1/4 x 1/4 the size of the full resolution video decoder.
Claim 22
Dependent Claim
68 words
The digital picture-in-picture decoder circuit of claim 21, further comprising a second reduced resolution video decoder coupled to the postprocessing circuit for decoding a reduced resolution version of a third picture; and wherein the post processor circuit operates to combine the reduced resolution version of the third picture with the first full resolution picture and the reduced resolution version of the second picture to form the single picture.
Claim 23
Dependent Claim
88 words
The digital picture-in-picture decoder circuit of claim 20, wherein the second set of digital video data includes a plurality of macroblocks, each macroblock including a plurality of DCT coefficients; and wherein the first reduced resolution video decoder comprises: preparser means for receiving the second set of digital video data and for removing from each macroblock DCT coefficients that exceed a preselected maximum number of DCT coefficients per macroblock; and a channel buffer coupled to the preparser means for temporarily storing the video data output by the preparser means.
Claim 24
Dependent Claim
83 words
The digital picture-in-picture decoder circuit of claim 23, wherein the first reduced resolution video decoder further comprises: a syntax parser and variable length decoder circuit coupled to the channel buffer for variable length decoding the second set of digital video data; a downsampler coupled to the syntax parser and variable length decoder circuit for downsampling the variable length decoded video data to thereby reduce the amount of resolution of the second picture and the amount of video data used to represent second picture.
Claim 25
Independent Claim
85 words
A method of decoding variable length encoded digital video data including slice stuffing data, start code zero stuffing data, and macroblocks, the macroblocks representing pictures, to a resolution less than the full resolution of the pictures, the method comprising the steps of: receiving the digital video data; parsing the digital video data to identify bit slice stuffing and start code zero stuffing data; discarding the bit slice stuffing data and start code zero stuffing data; and storing the remaining video data in a channel buffer.
Claim 26
Dependent Claim
34 words
The method of claim 25, further comprising the steps of: variable length decoding the video data stored in the channel buffer to generated fixed length video data; and downsampling the fixed length video data.
Claim 27
Independent Claim
86 words
A method of decoding digital video data including an interlaced picture, to a resolution less than the full resolution of the interlaced picture, the interlaced picture including a plurality of macroblocks encoded in accordance with one of a field DCT basis or a frame DCT basis, the method comprising the steps of: downsampling the macroblocks encoded on a field DCT basis on a field basis; downsampling the macroblocks encoded on a frame DCT basis on a frame basis; storing the downsampled macroblocks in a frame buffer.
Claim 28
Dependent Claim
28 words
The method of claim 27, wherein the video data further comprises a non-interlaced picture, the method comprising the steps of: downsampling the non-interlaced picture on a frame basis.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.