EP0704893A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Improved device planarity
Assignee: Texas Instruments Inc
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Filing: 1995-09-21
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Granted: —
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Expires: 2015-09-21
Abstract
Abstract A semiconductor device and process for making the same are disclosed which use reticulated conductors and a width-selective planarizing interlevel dielectric (ILD) deposition process to improve planarity of an interconnect layer. Reticulated conductor 52 is used in place of a solid conductor where the required solid conductor width would be greater than a process and design dependent critical width (conductors smaller than the critical width may be planarized by an appropriate ILD deposition). The reticulated conductor is preferably formed of integrally-formed conductive segments with widths less than the critical width, such that an ILD 32 formed by a process such as a high density plasma oxide deposition (formed by decomposition of silane in an oxygen-argon atmosphere with a back-sputtering bias) or spin-coating planarizes the larger, reticulated conductor as it would a solid conductor of less than critical width. Using such a technique, subsequent ILD planarization steps by, e.g., chemical mechanic polishing or etchback, may be reduced or avoided entirely.
Inventors
- 👤 Manoj Kumar Jain
- 👤 Michael Francis Chisholm
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-10 02:25
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43; H10P; H10P95/00; H10P95/06; H10P95/062; H10W20/01; H10W20/031; H10W20/071; H10W20/092
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
132 words
A method of constructing a planarized layer over a patterned conductor and adjacent regions on a semiconductor device, said method comprising: depositing a layer of conducting material on a substrate; removing said layer of conducting material in a predetermined region upon said substrate, such that a location for and peripheral walls for said conductor are defined; removing said layer of conducting material from at least one region within said predetermined region to form internal and/or notch walls for said conductor, such that the current-carrying capability for said conductor amongst at least two integrally-formed conducting segments of smaller minimum horizontal dimension than said conductor are divided; and forming an insulating layer over said conductor and said substrate which selectively planarizes features in order of smallest to largest based on a minimum horizontal dimension.
Claim 2
Dependent Claim
17 words
The method of Claim 1, wherein the forming an insulating layer step comprises depositing said insulating layer.
Claim 3
Dependent Claim
27 words
The method of Claim 1 or Claim 2, wherein said forming an insulating layer step comprises depositing silicon dioxide by a method of simultaneous CVD and sputtering.
Claim 4
Dependent Claim
33 words
The method of Claim 2, further comprising depositing an insulating seed layer over said conductor and said substrate, prior to said depositing silicon dioxide by a method of simultaneous CVD and back-sputtering step.
Claim 5
Independent Claim
28 words
The method of any preceding claim, further comprising depositing a CVD insulating layer over said conductor and said substrate, subsequent to the step of forming an insulating layer.
Claim 6
Independent Claim
13 words
The method of any preceding claim, further comprising chemical-mechanical polishing said insulating layer.
Claim 7
Independent Claim
22 words
The method of any preceding claim, further comprising forming said conducting segments to a minimum design rule specification for said semiconductor device.
Claim 8
Independent Claim
13 words
The method of any preceding claim, further comprising performing the removing steps simultaneously.
Claim 9
Independent Claim
15 words
The method of any preceding claim, further comprising forming said layer as a planarised dielectric.
Claim 10
Independent Claim
156 words
The method of any of Claims 1 to 8 for forming a planarized insulated interconnection layer on a semiconductor device, wherein said depositing step comprises: depositing a first layer of conducting material on the substrate; the removing steps comprise removing sections of said first layer of conducting material in a predetermined pattern, thereby forming a plurality of conducting regions, at least one of said conducting regions being a reticulated conductor, said reticulated conductor comprising a set of integrally-formed conducting segments which provide multiple conducting paths between opposing ends of said reticulated conductor; and the method further comprising depositing and patterning a second layer of conducting material over a top surface of said insulating layer, whereby said top surface of a portion of said insulating layer in the immediate vicinity of said reticulated conductor have improved planarization as compared to a top surface of a similar insulating layer overlying a non-reticulated conductor of equivalent length and resistivity.
Claim 11
Dependent Claim
161 words
A metallization structure on a semiconductor device, said structure comprising: a plurality of first conducting regions formed on a substrate, at least one of said first conducting regions being a non-reticulated conductor and at least one of said first conducting regions being a reticulated conductor, said reticulated conductor comprising a set of conducting segments connected to provide multiple conducting paths between opposing ends of said reticulated conductor; at least one insulating layer overlying said first conducting regions and said substrate, the uppermost of said insulating layers providing a top surface which is locally planar to at least 3000 Å; and a plurality of second conducting regions formed over said insulating layers, at least one of said second conducting regions electrically connected to at least one of said first conducting regions through said insulating layers; whereby planarity of said insulating layers is at least partially effected by use of said reticulated conductor instead of a non-reticulated conductor of equivalent resistivity and length.
Claim 12
Dependent Claim
29 words
The structure of Claim 11, wherein said conducting segments of said reticulated conductor are formed at a size and/or spacing equivalent to minimum design rules for said semiconductor device.
References Cited (Backward Citations)
No citation records indexed.
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