Patent US5321752A successfully refreshed from Google Patents.
EP0701277A2
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Interconnection method using a porous insulator for line to line capacitance reduction
Assignee: Texas Instruments Inc
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Filing: 1995-05-29
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Granted: —
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Expires: 2015-05-29
Abstract
Abstract An interconnect structure and method is described herein. First, interconnect lines 14a-d are formed on a semiconductor body 10. Then, a dielectric layer 20 is coated over the semiconductor body and the interconnect lines 14a-d to a thickness sufficient to more than fill the gaps between adjacent interconnect lines. The dielectric layer 20 is baked and then cured at a elevated temperature greater than the baking temperature. By using baking, then curing, the dielectric layer 20 inside the gaps has a lower density than that above interconnect lines and that in open fields. The removal of dielectric layer from the top of the interconnect lines by etchback is optional. Finally, a layer of silicon dioxide 12 is deposited over the interconnect lines 14a-d and the dielectric layer 20. In one embodiment, contact vias 11 are then etched through the silicon dioxide 12 and dielectric layer 20 to the interconnect lines 14a-c. Preferably, the dielectric material is spun on. One advantage of the invention is providing a metallization scheme that reduces line-to-line capacitance. A further advantage of the invention is providing a metallization scheme that reduces crosstalk and power dissipation. A further advantage of the invention is providing a dielectric layer between interconnect lines having a lower density and a lower dielectric constant than dense silicon dioxide.
Inventors
- 👤 Shin-Puu Jeng
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 14:12
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/692; H10P14/6921; H10P14/6922; H10P14/6925; H10P14/63; H10P14/6326; H10P14/6342; H10P14/65; H10P14/6502; H10P14/6506; H10P14/6516; H10P14/6548; H10P14/66; H10P14/665; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/072; H10W20/093; H10W20/097; H10W20/40; H10W20/45; H10W20/46; H10W20/48; H10W20/495; H10W20/098
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
50 words
A method of making an interconnect layer in a semiconductor device with a reduction in line-to-line capacitance, comprising: a. forming semiconductor elements on a semiconductor body; b. coating a dielectric layer over the semiconductor body and said semiconductor elements; c. baking said dielectric layer; and d. planarizing said dielectric layer.
Claim 2
Dependent Claim
59 words
The method of Claim 1, wherein said method further includes curing said dielectric layer at an elevated temperature to form a dielectric between closely spaced semiconductor elements which is less dense than said dielectric between relatively farther spaced semiconductor elements and in which said dielectric between said closely spaced semiconductor elements has a dielectric constant of less than 3.7.
Claim 3
Dependent Claim
25 words
The method of Claim 2, wherein said curing includes curing in a furnace at a temperture in a range of 200° C to 700° C.
Claim 4
Dependent Claim
26 words
The method of Claim 1, wherein said method further includes depositing a oxide liner by plasma deposition over said semiconductor elements and below said dielectric layer.
Claim 5
Dependent Claim
25 words
The method of Claim 1, wherein said baking is by a hot plate at a temperature in a range from room temperture to 500° C.
Claim 6
Dependent Claim
17 words
The method of Claim 2, wherein said curing is at a temperature is less than 400° C.
Claim 7
Dependent Claim
19 words
The method of Claim 1, wherein said method includes forming a moisture resistant cap material above said dielectric layer.
Claim 8
Dependent Claim
28 words
The method of Claim 1, wherein said method further includes removing said dielectric layer over said plurality of semiconductor elements and in open areas in said semiconductor body.
Claim 9
Dependent Claim
12 words
The method of Claim 1, wherein said planarizing includes chemical mechanical polish.
Claim 10
Independent Claim
83 words
A method of making an interconnect layer in a semiconductor device with a reduction in line-to-line capacitance, comprising: a. forming interconnect lines on a semiconductor body with a first and a second of said lines being spaced at less than one and one-half line width and with a third line being spaced from said second line by at least three line widths; b. coating a dielectric layer over said semiconductor body and said plurality of interconnect lines; and c. baking said dielectric layer.
Claim 11
Dependent Claim
61 words
The method of Claim 10, wherein said method further includes curing said dielectric layer at an elevated temperature to form a dielectric between said first and second lines which is less dense than said dielectric between said second and third line and in which said dielectric between said first and said second lines has a dielectric constant of less than 3.7.
Claim 12
Dependent Claim
25 words
The method of Claim 11, wherein said curing includes curing in a furnance at a temperture in a range of 200° C to 700° C.
Claim 13
Dependent Claim
27 words
The method of Claim 10, wherein said method further includes etching said dielectric layer to decrease the density of the dielectric between said first and second lines.
Claim 14
Dependent Claim
17 words
The method of Claim 10, wherein said forming a dielectric layer includes spinning on said dielectric layer.
Claim 15
Dependent Claim
28 words
The method of Claim 10, wherein said method further includes removing said dielectric layer over said plurality of interconnect lines and in open areas in said semiconductor body.
Claim 16
Dependent Claim
25 words
The method of Claim 10, wherein said method further includes forming a silicon dioxide layer over said plurality of interconnect lines and said dielectric layer.
Claim 17
Dependent Claim
27 words
The method of Claim 16, wherein said method further includes forming contact vias through said silicon dioxide layer and dielectric layer to the plurality of interconnect lines.
Claim 18
Dependent Claim
21 words
The method of Claim 10, wherein said baking is at a temperature in the range from room temperture to 500° C.
Claim 19
Dependent Claim
16 words
The method of Claim 11, wherein said curing is at a temperature less than 400° C.
Claim 20
Dependent Claim
19 words
The method of Claim 10, wherein said method includes forming a moisture resistant cap material above said dielectric layer.
Claim 21
Independent Claim
92 words
A method of making an interconnect layer in a semiconductor device with a reduction in line-to-line capacitance, comprising: a. forming semiconductor elements on a semiconductor body; b. depositing an oxide liner by plasma deposition over said semiconductor elements; c. spin-coating a dielectric layer over said oxide liner; d. baking said dielectric layer by a hot plate at a temperature in a range from room temperture to 500° C; e. forming a moisture resistant cap material above said dielectric layer; and f. planarizing said moisture resistant cap material by a chemical mechanical polish.
Claim 22
Dependent Claim
59 words
The method of Claim 21, wherein said method further includes curing said dielectric layer at an elevated temperature to form a dielectric between closely spaced semiconductor elements which is less dense than said dielectric between relatively farther spaced semiconductor elements and in which said dielectric between said closely spaced semiconductor elements has a dielectric constant of less than 3.7.
Claim 23
Dependent Claim
25 words
The method of Claim 22, wherein said curing includes curing in a furnance at a temperture in a range of 200° C to 700° C.
References Cited (Backward Citations)
No citation records indexed.
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