Low threshold voltage, high performance junction transistor

Claim 2

A MOS device on a semiconductor substrate which has an upper surface, the MOS device comprising: a retrograde well region in said semiconductor substrate extending downward from said upper surface and having a graded concentration of dopant of the first conductivity type such that the dopant concentration is greater near the bottom of the well region; source and drain regions of a second conductivity type which extend from the semiconductor substrate surface into the said retrograde well region; a channel region located between the source and drain regions; and a gate positioned over the channel region, wherein the MOS device has an on current and an off current and the ratio of on current to off current is not greater than about 10⁵, and wherein the dopant concentration proximate the bottom of the retrograde well is sufficiently high to diminish the likelihood of punch through.

Claim 3

The MOS device of claim 1 or 2, wherein the device has a gate threshold voltage of between about ± 150 mV.

Claim 4

The MOS device of claim 1 or 2, wherein the concentration of the first conductivity type dopant in the channel region is at most about 1 x 10¹⁶ atoms/cm³.

Claim 5

The MOS device of claim 4, wherein the concentration of the first conductivity type dopant in the channel region is between about 1 x 10¹⁴ and 1 x 10¹⁶ atoms/cm³.

Claim 6

The MOS device of claim 4, further comprising a counterdopant in the channel region.

Claim 7

The MOS device of claim 1 or 2, wherein the device has a tunable gate threshold voltage.

Claim 8

The MOS device of claim 7, wherein the gate threshold voltage is tunable by back biasing.

Claim 9

The MOS device of claim 7, further comprising a floating gate capable of tuning the device's threshold voltage.

Claim 10

The MOS device of claim 1, wherein the dopant concentration in the buried electrode is at least about 1 x 10¹⁶ atoms/cm³.

Claim 11

The MOS device of claim 10, wherein the dopant concentration in the buried electrode is between about 1 x 10¹⁶ and 1 x 10¹⁸ atoms/cm³.

Claim 12

The MOS device of claim 1, wherein the buried electrode has side boundaries which abut the facing edges of the source and drain regions.

Claim 13

The MOS transistor of claim 1, wherein the dopant concentration in the buried electrode is between about 10 and 100 times greater than an average dopant concentration in the bulk region.

Claim 14

The MOS device of claim 2, wherein the local dopant concentration proximate the bottom of the retrograde well region is at least about 1 x 10¹⁶ atoms/cm³.

Claim 15

The MOS device of claim 14, wherein the local dopant concentration proximate the bottom of the retrograde well region is between about 1 x 10¹⁶ and 1 x 10¹⁸ atoms/cm³.

Claim 16

The MOS transistor of claim 2, wherein the dopant concentration proximate the bottom of the retrograde well region is between about 10 and 100 times greater than a dopant concentration in the channel region.

Claim 17

The MOS device of claim 2, wherein said source and drain regions include (a) source and drain plug regions extending from the semiconductor substrate surface into said retrograde well region by a first predefined distance; and (b) source and drain tip regions extending toward one another along the semiconductor substrate surface from facing edges of the source and drain plug regions, the tip regions extending into said retrograde well region by a second predefined distance which is less than the first predefined distance.

Claim 19

The method of claim 18, wherein the dopant concentration in the buried electrode region is between about 1 x 10¹⁷ and 1 x 10¹⁸ atoms/cm³.

Claim 20

The method of claim 18, wherein the channel region has a concentration of dopant atoms of the first conductivity type that is not greater than about 1 x 10¹⁶ atoms/cm³.

Claim 21

The method of claim 20, wherein the channel region includes a concentration of dopant atoms of the first conductivity type that is between about 1 x 10¹⁴ and 1 x 10¹⁶ atoms/cm³.

Claim 22

The method of claim 18, wherein the step of forming a bulk region includes a separate step of forming said buried electrode.

Claim 23

The method of claim 22, wherein said step of forming the buried electrode is conducted at a dose of between about 5 x 10¹² to 1 x 10¹³ atoms/cm² and at an energy of between about 80-120 keV.

Claim 24

The method of claim 22, wherein the step of forming the bulk region includes at least three implant steps conducted at energies and dosages sufficient to define a buried electrode within a well region.

Claim 25

The method of claim 18, wherein the step of forming a bulk region includes a single implant at an energy and dose sufficient to produce a retrograde well.

Claim 26

A MOS device on a semiconductor substrate which has an upper surface, the MOS device comprising: a bulk region in said semiconductor substrate extending downward from said upper surface and having an average concentration of dopant of a first conductivity type; source and drain regions of a second conductivity type extending from the semiconductor substrate surface into said bulk region by a predefined distance; a channel region located between the source and drain regions; a buried electrode of the first conductivity type within the bulk region having an upper boundary disposed above the predefined distance, said buried electrode having a dopant concentration that is greater than the average dopant concentration in the bulk region; and a gate positioned over the channel region, wherein the MOS device has an on current and an off current and the ratio of on current to off current is not greater than about 10⁵, and wherein the buried electrode dopant concentration is sufficiently high to allow the MOS device to be tuned such that an applied back bias of 1 volt will shift the device's threshold voltage by between about 50 and 300 millivolts.

Claim 27

The MOS device of claim 26, wherein the buried electrode dopant concentration is sufficiently high to allow the MOS device to be tuned such that an applied back bias of 1 volt will shift the device's threshold voltage by between about 75 and 200 millivolts.

Claim 28

The MOS device of claim 27, wherein the buried electrode dopant concentration is sufficiently high to allow the MOS device to be tuned such that an applied back bias of 1 volt will shift the device's threshold voltage by about 100 millivolts.

Claim 29

The MOS device of claim 26, wherein the device has a gate threshold voltage of between about ± 150 mV.

Claim 30

The MOS device of claim 26, wherein the dopant concentration in the channel region is at most about 1 x 10¹⁶ atoms/cm³.

Claim 31

The MOS transistor of claim 26, wherein the dopant concentration in the buried electrode is between about 10 and 100 times greater than an average dopant concentration in the bulk region.