EP0697716A2
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EP
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Method for forming concurrent top oxides using reoxidized silicon
Assignee: Motorola Solutions Inc
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Filing: 1995-07-17
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Granted: —
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Expires: 2015-07-17
Abstract
Abstract A stack of oxide (16) and silicon nitride (18) is grown/deposited over a patterned polysilicon line, which typically acts as a bottom capacitor plate. A thin layer of amorphous or polycrystalline silicon (20) is deposited over the blanket silicon nitride film. The thickness of the deposited silicon layer must be optimized according to the final amount of oxide desired over the silicon nitride, which will be roughly twice the thickness of the deposited silicon film. The oxide/nitride/silicon stack is then patterned and etched, stopping either at or underneath the bottom oxide. Any subsequent cleaning in potentially oxide-etching chemistries (including HF) is done with the protective silicon deposit on top of the silicon nitride. The entire structure is then thermally oxidized, transforming the deposited silicon into silicon oxide (30). Where the structure has been cleared down to the substrate by etching, a second gate oxide is simultaneously formed.
Inventors
- 👤 Bich-Yen Nguyen
- 👤 Sergio A. Ajuria
- 👤 Wayne Paulson
- 👤 Jon Dahm
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 03:29
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D64/00; H10D64/01; H10D64/021; H10D64/031; H10D64/035
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
181 words
A method for forming concurrent top oxides, comprising the steps of: providing a semiconductor substrate (12); providing a polysilicon layer (14) overlying a first portion the semiconductor substrate; forming a first dielectric layer (16) overlying the polysilicon layer and a second portion of the semiconductor substrate; forming a second dielectric layer (18) overlying the first dielectric layer; forming an amorphous silicon layer (20) overlying the second dielectric layer to form a stack of amorphous silicon, second and first dielectric layers; patterning the stack of amorphous silicon, second and first dielectric layers to form a patterned stack and to expose a third portion of the semiconductor substrate; thermally oxidizing the amorphous silicon layer of the patterned stack to convert the amorphous silicon layer into a thermal oxide layer (30) having a first thickness, wherein the second dielectric layer acts as an oxidation stop for the patterned stack; and contemporaneously thermally oxidizing a top surface of the third portion of the semiconductor substrate to form a gate oxide (32) having a second thickness, wherein the second thickness is independent of the first thickness.
Claim 2
Independent Claim
180 words
A method for forming concurrent top oxides, comprising the steps of: providing a patterned substrate (12); providing a floating gate polysilicon layer (14) overlying a first portion the patterned substrate; forming a first oxide layer (16) overlying the floating gate polysilicon layer and a second portion of the patterned substrate; forming a nitride layer (18) overlying the first oxide layer; forming an amorphous silicon layer (20) overlying the nitride layer to form a stack of amorphous silicon, nitride and first oxide; patterning the stack of amorphous silicon, nitride and first oxide to form a patterned stack and to expose a third portion of the patterned substrate; thermally oxidizing the amorphous silicon layer of the patterned stack to convert the amorphous silicon layer into a second oxide layer (30) having a first thickness, wherein the nitride layer acts as an oxidation stop for the patterned stack; and contemporaneously thermally oxidizing a top surface of the third portion of the patterned substrate to form a gate oxide (32) having a second thickness, wherein the second thickness is independent of the first thickness.
Claim 3
Dependent Claim
32 words
The method of claim 1 or 2, wherein the step of thermally oxidizing the amorphous silicon layer is performed at a temperature lower than an oxidation temperature of the second dielectric layer.
Claim 4
Independent Claim
121 words
A method for forming an interpolysilicon dielectric for a semiconductor device, comprising the steps of: providing a patterned silicon substrate; providing a floating gate polysilicon (14) overlying a first portion the patterned silicon substrate; forming a nitride layer (22) overlying the floating gate polysilicon to form a stack comprising the nitride layer and the floating gate polysilicon; patterning the stack to form a patterned stack having a sidewall; forming a conformal amorphous silicon layer (26') overlying the patterned stack and a second portion of the patterned silicon substrate; and thermally oxidizing the conformal amorphous silicon layer to convert the conformal amorphous silicon layer into a thermal oxide layer (30') overlying the patterned stack and covering the sidewall of the patterned stack.
Claim 5
Dependent Claim
40 words
The method of claim 4, further comprising the step of removing a portion of the thermal oxide layer overlying the patterned stack to leave a remaining portion along the sidewall of the patterned stack, the remaining portion forming a spacer.
Claim 6
Dependent Claim
79 words
The method of claim 4, further comprising the steps of: forming a second oxide layer (24) overlying the floating gate polysilicon to form a stack comprising the second oxide layer and the floating gate polysilicon; and exposing a second portion of the patterned silicon substrate during the step of patterning the stack, such that during the thermal oxidizing step, a second gate oxide (32) is formed contemporaneously with converting the conformal amorphous silicon layer into the thermal oxide layer.
Claim 7
Dependent Claim
36 words
The method of claim 1, 2 or 6, wherein the step of forming the amorphous silicon layer is performed through a chemical vapor deposition at a temperature substantially in a range of 400 to 560 °C.
Claim 8
Independent Claim
139 words
A method for forming an inflatable spacer for a semiconductor device, comprising the steps of: providing a patterned silicon substrate; providing a floating gate polysilicon (14'), having a sidewall, overlying a first portion the patterned silicon substrate; forming a nitride layer (54) overlying the floating gate polysilicon and covering the sidewall of the floating gate polysilicon; forming a conformal amorphous silicon layer (26''), having a first thickness, overlying the nitride layer; removing a top portion of the conformal amorphous silicon layer to leave a remaining portion (56) along the sidewall, the remaining portion forming a spacer; and thermally oxidizing the remaining portion of the conformal amorphous silicon layer to convert it into a thermal oxide layer forming the inflatable spacer (58) covering the sidewall, wherein the inflatable spacer has a second thickness substantially twice that of the first thickness.
References Cited (Backward Citations)
No citation records indexed.
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