EP0696111A2
Expired / Lapsed
EP
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A hitless path switching apparatus and method
Assignee: NTT Inc
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Filing: 1995-07-17
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Granted: —
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Expires: 2015-07-17
Abstract
Abstract A hitless path switching method without a bit loss. A bit error in the same digital line signals is continuously monitored independently of a predetermined data blocks of a working path (51) and a protection path (61). If a bit error occurs in the working path and no bit error occurs in the protection path, a switching trigger is produced and the switching from the working path to the protection path is performed on the data block basis. Only correct data are transferred to downstream apparatuses. A reliable hitless switching is achieved not only in response to a failure in its own path, but also in response to a bit error. Using data blocks of one frame length with an indicator for bit error check placed at its top makes an effective switching possible.
Inventors
- 👤 Nobuyuki Kawase
- 👤 Yoshiaki Yamabayashi
- 👤 Yoshihiko Uematsu
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 07:58
CPC Classifications
H; H04; H04B; H04B1/00; H04B1/74; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/062; H04J3/14; H04L; H04L1/00; H04L1/22; H04Q; H04Q11/00; H04Q11/04; H04Q11/0428; H04Q11/0478; H04J2203/00; H04J2203/0001; H04J2203/0051; H04J2203/0057; H04J2203/006; H04J2203/0073; H04J2203/0076; H04L12/00; H04L12/54; H04L12/56; H04L12/5601; H04L2012/5619; H04L2012/5625; H04L2012/5627; H04L2012/5638; H04L2012/5646; H04L2012/5647
Claims Analysis
Total Claims: 42
Claim 1
Independent Claim
425 words
A hitless path switching apparatus which receives same line signals incoming through a first path and a second path in the form of a stream of data blocks each including an indicator for bit error check, and supplies one of the same line signals to a third path by hitless switching, thereby allotting one of the first path and the second path to a working path and the other to a protection path, said hitless path switching apparatus characterized by comprising: a first signal terminating circuit connected to said first path for receiving one of the same line signals and outputting a first line signal; a second signal terminating circuit connected to said second path for receiving the other of the same line signals and outputting a second line signal; a first bit error detecting circuit for detecting a bit error of each said data blocks of said first line signal using said indicator for bit error check; a second bit error detecting circuit for detecting a bit error of each said data blocks of said second line signal using said indicator for bit error check; a first delay circuit for delaying said first line signal by at least one data block interval; a second delay circuit for delaying said second line signal by at least one data block interval; a phase difference detecting circuit for detecting a phase difference between said data block of said first line signal and said data block of said second line signal; a phase adjusting circuit for adjusting the phase difference detected by said phase difference detecting circuit to match phases of said two data blocks, and supplying in-phase data blocks of said first line signal and of said second line signal to said first delay circuit and second delay circuit, respectively; a switching circuit for selectively supplying said third path with one of said first line signal outputted from said first delay circuit and said second line signal outputted from said second delay circuit; and correlation monitoring circuit for supplying said switching circuit with a switching control signal to make said switching circuit supply said third path with said second line signal outputted from said second delay circuit, if said first bit error detecting circuit detects a bit error in a data block of said first line signal and said second bit error detecting circuit detects no bit error in corresponding data block of said second line signal when said first path is allotted to said working path and said second path is allotted to said protection path.
Claim 2
Dependent Claim
109 words
The hitless path switching apparatus as claimed in claim 1, characterized in that said signal terminating circuit comprises failure detecting means for detecting a failure occurring in said first path and said second path by monitoring said line signals, and said correlation monitoring circuit provides said switching circuit with said switching control signal to switch said second path to said working path and said first path to said protection path regardless of a bit error occurrence in said data block, if the failure is detected at said first path when said first path is allotted to said working path and said second path is allotted to said protection path.
Claim 3
Dependent Claim
47 words
The hitless path switching apparatus as claimed in claim 2, characterized in that said failure is the alarm signals such as loss of signal, loss of frame, alarm indication signal, and so on, defined in ITU-T Recommendation G. 70X and the ANSI SONET (Synchronous Optical NETwork) standard.
Claim 4
Dependent Claim
34 words
The hitless path switching apparatus as claimed in claim 3, characterized in that said indicator for bit error check is a B3 byte defined in ITU-T Recommendation G. 70X and the ANSI SONET standard.
Claim 5
Dependent Claim
34 words
The hitless path switching apparatus as claimed in claim 3, characterized in that said indicator for bit error check is a B2 byte defined in ITU-T Recommendation G. 70X and the ANSI SONET standard.
Claim 6
Dependent Claim
28 words
The hitless path switching apparatus as claimed in claim 1, characterized in that each of said data blocks has said indicator for bit error check at its top.
Claim 7
Dependent Claim
34 words
The hitless path switching apparatus as claimed in claim 6, characterized in that a transferring timing of said switching control signal from correlation monitoring circuit is immediately after said indicator for bit error check.
Claim 8
Dependent Claim
47 words
The hitless path switching apparatus as claimed in claim 7, characterized in that said failure is the alarm signals such as loss of signal, loss of frame, alarm indication signal, and so on, defined in ITU-T Recommendation G. 70X and the ANSI SONET (Synchronous Optical NETwork) standard.
Claim 9
Dependent Claim
34 words
The hitless path switching apparatus as claimed in claim 8, characterized in that said indicator for bit error check is a B3 byte defined in ITU-T Recommendation G. 70X and the ANSI SONET standard.
Claim 10
Dependent Claim
34 words
The hitless path switching apparatus as claimed in claim 8, characterized in that said bit indicator for error check is a B2 byte defined in ITU-T Recommendation G. 70X and the ANSI SONET standard.
Claim 11
Dependent Claim
27 words
The hitless path switching apparatus as claimed in claim 1, characterized in that said data blocks are a VC (Virtual Container) frame defined in ITU-T Recommendation G.70X.
Claim 12
Dependent Claim
54 words
The hitless path switching apparatus as claimed in claim 11, characterized in that each of said data blocks is a data block of one frame length having at its top a B3 byte defined in ITU-T Recommendation G. 70X, and a transferring timing of said switching control signal is immediately after said B3 byte.
Claim 13
Dependent Claim
41 words
The hitless path switching apparatus as claimed in claim 1, characterized in that said data blocks are one of an STS SPE (Synchronous Transport Signal Synchronized Payload Environment) frame, and VT (virtual Tributary) SPE frame defined in the ANSI SONET standard.
Claim 14
Dependent Claim
49 words
The hitless path switching apparatus as claimed in claim 13, characterized in that each of said data blocks is a data block of one frame length having at its top a B3 byte defined in the ANSI SONET standard, and said transferring timing is immediately after said B3 byte.
Claim 15
Dependent Claim
29 words
The hitless path switching apparatus as claimed in claim 1, characterized in that said data blocks are an STM (Synchronous Transport Module) frame defined in ITU-T Recommendation G. 70X.
Claim 16
Dependent Claim
54 words
The hitless path switching apparatus as claimed in claim 15, characterized in that each of said data blocks is a data block of one frame length having at its top a B2 byte defined in ITU-T Recommendation G. 70X, and a transferring timing of said switching control signal is immediately after said B2 byte.
Claim 17
Dependent Claim
25 words
The hitless path switching apparatus as claimed in claim 1, characterized in that said data blocks are an STS frame defined in the ANSI standard.
Claim 18
Dependent Claim
54 words
The hitless path switching apparatus as claimed in claim 17, characterized in that each of said data blocks is a data block of one frame length having at its top a B2 byte defined in the ANSI SONET standard, and a transferring timing of said switching control signal is immediately after said B2 byte.
Claim 19
Dependent Claim
28 words
The hitless path switching apparatus as claimed in claim 1, characterized in that said data blocks are an ATM (Asynchronous Transfer Mode) cell defined in ITU-T Recommendation I.432.
Claim 20
Dependent Claim
30 words
The hitless path switching apparatus as claimed in claim 19, characterized in that said indicator for bit error check is a HEC (Header Error Control) byte in said ATM cell.
Claim 21
Dependent Claim
42 words
The hitless path switching apparatus as claimed in claim 19, characterized in that said indicator for bit error check is obtained by performing bit interleave parity computation over all bits in a header area and an information area of said ATM cell.
Claim 22
Dependent Claim
318 words
A hitless path switching method which receives same line signals incoming through a first path and a second path in the form of a stream of data blocks each including an indicator for bit error check, and supplies one of the same line signals to a third path by hitless switching, thereby allotting one of the first path and the second path to a working path and the other to a protection path, said hitless path switching method characterized by comprising the steps of: receiving one of the same line signals and outputting a first line signal; receiving the other of the same line signals and outputting a second line signal; detecting a bit error of each said data blocks of said first line signal using said indicator for bit error check; detecting a bit error of each said data blocks of said second line signal using said indicator for bit error check; detecting a phase difference between said data block of said first line signal and said data block of said second line signal; adjusting the phase difference to match phases of said two data blocks, and outputting in-phase data blocks of said first line signal and of said second line signal; delaying said first line signal by at least one data block interval; delaying said second line signal by at least one data block interval; selectively supplying said third path with one of said first line signal and said second line signal which have been delayed; and producing switching control signal for supplying said third path with said second line signal which has been delayed, if a bit error is detected in a data block of said first line signal and no bit error is detected in the corresponding data block of said second line signal when said first path is allotted to said working path and said second path is allotted to said protection path.
Claim 23
Dependent Claim
90 words
The hitless path switching method as claimed in claim 22, characterized by further comprising the steps of detecting a failure occurring in said first path and said second path by monitoring said line signals, and switching said second path to said working path and said first path to said protection path regardless of a bit error occurrence in said data block, if the failure is detected at said first path when said first path is allotted to said working path and said second path is allotted to said protection path.
Claim 24
Dependent Claim
47 words
The hitless path switching method as claimed in claim 23, characterized in that said failure is the alarm signals such as loss of signal, loss of frame, alarm indication signal, and so on, defined in ITU-T Recommendation G. 70X and the ANSI SONET (Synchronous Optical NETwork) standard.
Claim 25
Dependent Claim
34 words
The hitless path switching method as claimed in claim 24, characterized in that said indicator for bit error check is a B3 byte defined in ITU-T Recommendation G. 70X and the ANSI SONET standard.
Claim 26
Dependent Claim
34 words
The hitless path switching method as claimed in claim 24, characterized in that said indicator for bit error check is a B2 byte defined in ITU-T Recommendation G. 70X and the ANSI SONET standard.
Claim 27
Dependent Claim
28 words
The hitless path switching method as claimed in claim 22, characterized in that each of said data blocks has said indicator for bit error check at its top.
Claim 28
Dependent Claim
29 words
The hitless path switching method as claimed in claim 27, characterized in that a transferring timing of said switching control signal is immediately after said indicator bit error check.
Claim 29
Dependent Claim
47 words
The hitless path switching method as claimed in claim 28, characterized in that said failure is the alarm signals such as loss of signal, loss of frame, alarm indication signal, and so on, defined in ITU-T Recommendation G. 70X and the ANSI SONET (Synchronous Optical NETwork) standard.
Claim 30
Dependent Claim
34 words
The hitless path switching method as claimed in claim 29, characterized in that said indicator for bit error check is a B3 byte defined in ITU-T Recommendation G. 70X and the ANSI SONET standard.
Claim 31
Dependent Claim
34 words
The hitless path switching method as claimed in claim 29, characterized in that said indicator for bit error check is a B2 byte defined in ITU-T Recommendation G. 70X and the ANSI SONET standard.
Claim 32
Dependent Claim
27 words
The hitless path switching method as claimed in claim 22, characterized in that said data blocks are a VC (Virtual Container) frame defined in ITU-T Recommendation G.70X.
Claim 33
Dependent Claim
54 words
The hitless path switching method as claimed in claim 32, characterized in that each of said data blocks is a data block of one frame length having at its top a B3 byte defined in ITU-T Recommendation G. 70X, and a transferring timing of said switching control signal is immediately after said B3 byte.
Claim 34
Dependent Claim
41 words
The hitless path switching method as claimed in claim 22, characterized in that said data blocks are one of an STS SPE (Synchronous Transport Signal Synchronized Payload Environment) frame, and VT (virtual Tributary) SPE frame defined in the ANSI SONET standard.
Claim 35
Dependent Claim
49 words
The hitless path switching method as claimed in claim 34, characterized in that each of said data blocks is a data block of one frame length having at its top a B3 byte defined in the ANSI SONET standard, and said transferring timing is immediately after said B3 byte.
Claim 36
Dependent Claim
29 words
The hitless path switching method as claimed in claim 22, characterized in that said data blocks are an STM (Synchronous Transport Module) frame defined in ITU-T Recommendation G. 70X.
Claim 37
Dependent Claim
54 words
The hitless path switching method as claimed in claim 36, characterized in that each of said data blocks is a data block of one frame length having at its top a B2 byte defined in ITU-T Recommendation G. 70X, and a transferring timing of said switching control signal is immediately after said B2 byte.
Claim 38
Dependent Claim
25 words
The hitless path switching method as claimed in claim 22, characterized in that said data blocks are an STS frame defined in the ANSI standard.
Claim 39
Dependent Claim
54 words
The hitless path switching method as claimed in claim 38, characterized in that each of said data blocks is a data block of one frame length having at its top a B2 byte defined in the ANSI SONET standard, and a transferring timing of said switching control signal is immediately after said B2 byte.
Claim 40
Dependent Claim
28 words
The hitless path switching method as claimed in claim 22, characterized in that said data blocks are an ATM (Asynchronous Transfer Mode) cell defined in ITU-T Recommendation I.432.
Claim 41
Dependent Claim
30 words
The hitless path switching method as claimed in claim 40, characterized in that said indicator for bit error check is a HEC (Header Error Control) byte in said ATM cell.
Claim 42
Dependent Claim
42 words
The hitless path switching method as claimed in claim 40, characterized in that said indicator for bit error check is obtained by performing bit interleave parity computation over all bits in a header area and an information area of said ATM cell.
References Cited (Backward Citations)
No citation records indexed.
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