SOI-type semiconductor device with suppressed spread of depletion region

Claim 2

A device as set forth in claim 1, wherein semiconductor substrate is made of monocrystalline silicon.

Claim 3

A device as set forth in claim 1, wherein said insulating layer is made of silicon oxide.

Claim 4

A device as set forth in claim 1, wherein said semiconductor layer is made of monocrystalline silicon.

Claim 5

A device as set forth in claim 1, wherein said semiconductor substrate comprises: a first portion (1) in the proximity of said insulating layer, said first portion having an impurity concentration larger than approximately 1×10¹⁶/cm³; and a second portion (1a) apart from said insulating layer, said second portion having an impurity concentration smaller then approximately 1×10¹⁶/cm³.

Claim 6

A device as set forth in claim 1, wherein said semiconductor layer comprises a source region (3S), a channel region (3C) and a drain region (3D) of a MIS transistor.

Claim 7

A device as set forth in claim 6, wherein said at least one part of said semiconductor substrate is arranged beneath said source region and said drain region.

Claim 8

A device as set forth in claim 6, wherein said at least one part of said semiconductor substrate is arranged beneath said channel region.

Claim 9

A device as set forth in claim 6, further comprising: a first metal layer (9S) connected to said source region; a first wiring layer (8S) connected to said first metal layer, said first metal layer being wider than said first wiring layer; a second metal layer (9D) connected to said drain region; and a second wiring layer (8D) connected to said second metal layer, said second metal layer being wider than said second wiring layer.

Claim 10

A device as set forth in claim 1, wherein said semiconductor layer comprises a source region (3S-1), a channel region (3C-1) and a drain region (3D-1) of a first MIS transistor (Q₁), and a source region (3S-2), a channel region (3C-2) and a drain region (3D-2) of a second MIS transistor (Q₂), said drain region of said first MIS transistor being in common with said source region of said second MIS transistor.

Claim 11

A device as set forth in claim 10, wherein said at least one part of said semiconductor substrate is arranged beneath said source region and said drain region of said first MIS transistor and beneath said source region and said drain region of said second MIS transistor.

Claim 12

A device as set forth in claim 10, wherein said at least one part of said semiconductor substrate is arranged beneath said channel regions of said first and second MIS transistors.

Claim 13

A device as set forth in claim 10, further comprising: a first metal layer (9S-1) connected to said source region of said first MIS transistor; a first wiring layer (8S) connected to said first metal layer, said first metal layer being wider than said first wining layer; a second metal layer (9D-1, 9S-2) connected to said drain region of said first MIS transistor and said source region of said second MIS transistor; a third metal layer (9D-2) connected to said drain region of said second MIS transistor; and a second wiring layer (8D) connected to said third metal layer, said third metal layer being wider than said second wiring layer.

Claim 14

A device as set forth in claim 1, wherein said semiconductor substrate comprises: a first impurity region (1) of a first conductivity type having an impurity concentration larger than approximately 1×10¹⁶/cm³; a second impurity region (1a) of a second conductivity type opposite to said first conductivity type having an impurity concentration larger than approximately 1×10¹⁶/cm³; said semiconductor layer comprising a source region (3S-1), a channel region (3C-1) and a drain region (3D-1) of a first MIS transistor (Q n ) of said second conductivity type, and a drain region (3D-2), a channel region (3C-2) and a source region (3S-2) of a second MIS transistor (Q p ) of said first conductivity, said drain region of said first MIS transistor being connected to said drain region of said second MIS transistor.

Claim 15

A device as set forth in claim 14, further comprising: a first metal layer (9S-1) connected to said source region of said first MIS transistor; a first wiring layer (8S-1) connected to said first metal layer, said first metal layer being wider than said first wiring layer; a second metal layer (9D-1) connected to said drain region of said first MIS transistor; a third metal layer (3D-2) connected to said drain region of said second MIS transistor; a second wiring layer (8D-1, 8D-2) connected to said second and third metal layers, said second and third metal layer being wider than said third coiring layer; a fourth metal layer (9S-2) connected to said source region of said second MIS transistor; and a third wiring layer (8S-2) connected to said fourth metal layer, said fourth metal layer being wider than said third wiring layer.

Claim 16

A device as set forth in claim 1, wherein said semiconductor substrate comprises: a first impurity region (1) of a first conductivity type having an impurity concentration smaller than approximately 1×10¹⁶/cm³; a second impurity region (1a) of said first conductivity type formed on said first impurity region and in the proximity of said insulating layer, said second impurity region having an impurity concentration larger than approximately 1×10¹⁶/cm³; a third impurity region (W) of a second conductivity type opposite to said first conductivity type having an impurity concentration smaller than approximately 1×10¹⁶/cm³; a fourth impurity region of said second conductivity type formed on said third impurity region and in the proximity of said insulating layer, said fourth impurity region having an impurity concentration larger than approximately 1×10¹⁶/cm³; said semiconductor layer comprising a source region (3S-1), a channel region (3C-1) and a drain region (3D-1) of a first MIS transistor (Q n ) of said first conductivity type, formed above said second impurity region, and a drain region (3D-2), a channel region (3C-2) and a source region (3S-2) of a second MIS transistor (Q p ) of said second conductivity formed above said fourth impurity region, said drain region of said first MIS transistor being connected to said drain region of said second MIS transistor.

Claim 17

A device as set forth in claim 16, further comprising: a first metal layer (9S-1) connected to said source region of said first MIS transistor; a first wiring layer (8S-1) connected to said first metal layer, said first metal layer being wider than said first wiring layer; a second metal layer (9D-1) connected to said drain region of said first MIS transistor; a third metal layer (9D-2) connected to said drain region of said second MIS transistor; a second wiring layer (8D-1, 8D-2) connected to said second and third metal layers, said second and third metal layers being wider than said second wiring layer; a fourth metal layer (9S-2) connected to said source region of said second MIS transistor; and a third wiring layer (8S-2) connected to said fourth metal layer, said fourth metal layer being wider than said third wiring layer.

Claim 18

A device as set forth in claim 16, wherein said second impurity region is arranged beneath said source region and said drain region of said first MIS transistor, said fourth impurity region being arranged beneath said source region and said drain region of said second MIS transistor.

Claim 19

A device as set forth in claim 16, wherein said second impurity region is arranged beneath said channel region of said first MIS transistor, said fourth impurity region being arranged beneath said channel region of said second MIS transistor.

Claim 20

A semiconductor device comprising: a semiconductor substrate (1) of a first conductivity type having a first impurity concentration; an impurity layer (1') of said first conductivity type, being formed on said semiconductor substrate and having a second impurity concentration larger than said first impurity concentration; an insulating layer (2) formed on said impurity layer; and a semiconductor layer (3) formed on said insulating layer.

Claim 21

A device as set forth in claim 20, wherein said semiconductor layer comprises a source region (3S), a channel region (3C) and a drain region (3D) of a MIS transistor of a second conductivity type opposite to said first conductivity type.

Claim 22

A secmiconductor device comprising: a semiconductor substrate (1) of a first conductivity type; first and second impurity regions (1S, 1D) of said first conductivity type, being formed in said semiconductor substrate and having a larger impurity concentration than said semiconductor substrate; an insulating layer (2) formed on said semiconductor substrate; and a semiconductor layer (3) formed on said insulating layer, said semiconductor layer comprising a MIS transistor of a second conductivity type opposite to said first conductivity type including a source region (3S) above said first impurity region, a drain region (3D) above said second impurity region and a channel region (3C) between said source region and said drain region.

Claim 23

A semiconductor device comprising: a semiconductor substrate (1) of a first conductivity type; an impurity region (1C) of said first conductivity type, being formed in said semiconductor substrate and having a larger impurity concentration than said semiconductor substrate; an insulating layer (2) formed on said semiconductor substrate; and a semiconductor layer (3) formed on said insulating layer, said semiconductor layer comprising a MIS transistor of a second conductivity type opposite to said first conductivity type including a source region (3S), a drain region (3D) and a channel region (3C) above said impurity region between said source region and said drain region.

Claim 24

A semiconductor device comprising: a semiconductor substrate (1) of a first conductivity type connected to a first power supply terminal (GND); an impurity well region (W) of a second conductivity type opposite to said first conductivity type, being formed in said semiconductor substrate and connected to a second power supply terminal; an insulating layer (2) formed on said semiconductor substrate; and a semiconductor layer (3) formed on said insulating layer, said semiconductor layer comprising a first MIS transistor of said first conductivity type including a source region (1S-1), a drain region (1D-1) and a channel region (1C-1) therebetween arranged above said semiconductor substrate, and a second MIS transistor of said second conductivity type including a source region (1S-2), a drain region (1D-2) and a channel region (1C-2) therebetween arranged above said impurity well region.

Claim 25

A semiconductor device comprising: a semiconductor substrate (1) of a first conductivity type; a first rich impurity region (1') of said first conductivity type formed in said semiconductor substrate in a first area thereof, said rich first impurity region having a larger impurity concentration than said semiconductor substrate; an impurity well region (W) of a second conductivity type opposite to said first conductivity type, being formed in said semiconductor substrate in a second area thereof; a second rich impurity region (W') of said second conductivity type formed in said impurity well region, said second impurity region having a larger impurity concentration than said impurity well region; an insulating layer (2) formed on said semiconductor substrate; and a semiconductor layer (3) formed on said insulating layer, said semiconductor layer comprising: a first MIS transistor (Q n ) of said first conductivity type including a source region (1S-1), a drain region (1D-1) and a channel region (1C-1) therebetween, said first MIS transistor being arranged above said first rich impurity region; and a second MIS transistor (Q p ) of said second conductivity type including a source region (1S-2), a drain region (1D-2) and a channel region (1C-2) therebetween, said second MIS transistor being arranged above said second rich impurity region.

Claim 26

A semiconductor device comprising: a semiconductor substrate (1) of a first conductivity type; first and second rich impurity regions (1S-1, 1D-1) of said first conductivity type formed in said semiconductor substrate in a first area thereof, said rich first impurity regions having a larger impurity concentration than said semiconductor substrate; an impurity well region (W) of a second conductivity type opposite to said first conductivity type, being formed in said semiconductor substrate in a second area thereof; third and fourth rich impurity regions (1S-2, 1D-2) of said second conductivity type formed in said impurity well region, said third and fourth impurity regions having a larger impurity concentration than said impurity well region; an insulating layer (2) formed on said semiconductor substrate; and a semiconductor layer (3) formed on said insulating layer, said semiconductor layer comprising a first MIS transistor (Q n ) of said first conductivity type including a source region (1S-1) above said first rich impurity region, a drain region (1D-1) above said second rich impurity region and a channel region (1C-1) therebetween, and a second MIS transistor (Q p ) of said second conductivity type including a source region (1S-2) above said third rich impurity region, a drain region (1D-2) above said fourth rich impurity region and a channel region (1C-2) therebetween.

Claim 27

A semiconductor device comprising: a semiconductor substrate (1) of a first conductivity type; a first rich impurity region (1C-1) of said first conductivity type formed in said semiconductor substrate in a first area thereof, said rich first impurity region having a larger impurity concentration than said semiconductor substrate; an impurity well region (W) of a second conductivity type opposite to said first conductivity type, being formed in said semiconductor substrate in a second area thereof; a second rich impurity region (1C-2) of said second conductivity type formed in said impurity well region, said second impurity region having a larger impurity concentration than said impurity well region; an insulating layer (2) formed on said semiconductor substrate; and a semiconductor layer (3) formed on said insulating layer, said semiconductor layer comprising: a first MIS transistor (Q n ) of said first conductivity type including a source region (1S-1), a drain region (1D-1) and a channel region (1C-1) therebetween, said channel region of said first MIS transistor being arranged above said first rich impurity region; and a second MIS transistor (Q p ) of said second conductivity type including a source region (1S-2), a drain region (1D-2) and a channel region (1C-2) therebetween, said channel region of said second MIS transistor being arranged above said second rich impurity region.