EP0690487A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Methods for forming oxide films
Assignee: Advanced Micro Devices Inc
•
Filing: 1995-05-26
•
Granted: —
•
Expires: 2015-05-26
Abstract
Abstract High quality oxides utilized in tunnel oxides and CMOS gate oxides are formed using a process that includes annealing a semiconductor substrate, after the oxide has been formed, in an ambient comprised of NO to form a surface layer in the oxide containing a concentration of nitrogen. A high-quality tunnel oxide, suitable for EEPROM devices, is formed upon a surface region of a semiconductor body over a heavily-doped N+ layer by first oxidizing the semiconductor body to form an oxide upon the surface region of the semiconductor body over the heavily-doped N+ layer. Next, the semiconductor body is annealed, under a gettering ambient, to densify the oxide and to dope the oxide at its surface and for a portion thereinto near its surface with a gettering agent. The semiconductor body is then oxidized, under an oxidizing ambient, to thicken the oxide. The annealing step in NO improves characteristics for both the gate and tunnel oxides of the device at a temperature substantially reduced from prior art methods and in an ambient atmosphere containing significantly more NO. The NO anneal can be performed in a variety of ways including an RTP anneal, a furnace anneal and can be performed on processes where the oxides are formed using CVD and PECVD.
Inventors
- 👤 Dirk J. Wristers
- 👤 Dim-Lee Kwong
- 👤 Jim H. Fulford, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 02:13
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/0134; C; C23; C23C; C23C16/00; C23C16/56; H10B; H10B41/00; H10B41/30; H10B41/35; H10D64/60; H10D64/66; H10D64/68; H10D64/693; H10D64/01342; H10D64/01344; H10D64/01346; Y; Y10; Y10S; Y10S438/00; Y10S438/909; Y10S438/954
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
36 words
A method of forming an oxide film comprising the step of: exposing an oxide layer to an ambient atmosphere consisting essentially of NO, thereby forming a region in the oxide layer having a concentration of nitrogen.
Claim 2
Dependent Claim
49 words
In a process of fabricating a semiconductor device, the method of forming an improved oxide comprising the steps of: forming an oxide layer above a surface of a semiconductor substrate; and annealing the semiconductor substrate having the oxide layer in an ambient atmosphere comprised of more than 5% NO.
Claim 3
Dependent Claim
46 words
In a process of fabricating a semiconductor device, the method of forming an improved oxide comprising the steps of: forming an oxide layer on a surface of the semiconductor substrate; and annealing the semiconductor substrate in an ambient containing nitrogen at a temperature less than 1000°C.
Claim 4
Dependent Claim
30 words
The method as recited in claim 2, wherein the oxide is formed using a standard diffusion tube and the annealing step is performed in a rapid thermal anneal (RTA) system.
Claim 5
Dependent Claim
21 words
The method according to claim 4, wherein the annealing step is performed at temperatures ranging from 800° to about 1050° C.
Claim 6
Dependent Claim
24 words
The method according to claim 5, wherein the annealing step is performed for a time ranging from about 10 seconds to about three minutes.
Claim 7
Dependent Claim
28 words
The method as recited in claim 2, wherein the oxide is formed using a standard diffusion tube and the annealing step is performed in a standard diffusion tube.
Claim 8
Dependent Claim
22 words
The method according to claim 7, wherein the annealing step is performed at temperatures ranging from about 800° to about 1000° C.
Claim 9
Dependent Claim
16 words
The method according to claim 7, wherein the annealing step is performed for approximately 15 minutes.
Claim 10
Dependent Claim
29 words
The method as recited in claim 2, wherein the step of forming the oxide and the anneal step are performed using a plasma enhanced chemical vapor deposition (PECVD) process.
Claim 11
Dependent Claim
72 words
The method as recited in claim 2, further comprising the steps of: annealing the semiconductor substrate in an NO ambient using a chemical vapor deposition (CVD) system a first time to form a first oxide layer above said semiconductor substrate; and wherein the oxide layer is formed using the CVD system and wherein the semiconductor substrate is annealed in the NO ambient using the CVD system to form a third oxide layer.
Claim 12
Dependent Claim
51 words
The method as recited in claim 2, wherein the oxide is formed on the semiconductor substrate using a chemical vapor deposition (CVD) system; and wherein the anneal step is performed in the CVD system to form a second oxide layer adjacent to the oxide layer, the second oxide layer containing nitrogen.
Claim 13
Independent Claim
81 words
A method of fabricating a semiconductor device containing an oxide/nitride/oxide dielectric, comprising the steps of: forming a first oxide layer above a surface of a semiconductor substrate; annealing the semiconductor substrate having said first oxide layer in an ambient atmosphere composed substantially of NO; depositing a nitride layer on said first oxide layer; forming a second oxide layer on said nitride layer; annealing the semiconductor substrate having said first and second oxide layers in an ambient atmosphere consisting essentially of NO.
Claim 14
Dependent Claim
22 words
The method as recited in claim 2, wherein the semiconductor is annealed in an ambient atmosphere comprised of more than 10% NO.
Claim 15
Dependent Claim
22 words
The method as recited in claim 2, wherein the semiconductor is annealed in an ambient atmosphere comprised of more than 50% NO.
Claim 16
Dependent Claim
124 words
In an integrated circuit fabrication process, a method of forming a high quality oxide upon a surface region of a semiconductor body, comprising the steps of: oxidizing the semiconductor body a first time, under an ambient containing NO, to form a first oxide layer upon the surface region; annealing the semiconductor body a first time subsequent to the first oxidizing step, under a gettering ambient, to densify the first oxide layer and to dope the first oxide layer at its surface and for a portion thereinto near its surface with a gettering agent; and oxidizing the semiconductor body a second time, under an oxidizing ambient containing NO, to form a second oxide layer upon the first oxide layer, subsequent to the first annealing step.
Claim 17
Dependent Claim
166 words
In an integrated circuit fabrication process, a method of forming a high quality oxide upon a surface region of a semiconductor body, comprising the steps of: oxidizing the semiconductor body a first time, under an oxidizing ambient, to form a first oxide layer upon the surface region; annealing the semiconductor body a first time subsequent to the first oxidizing step, under a gettering ambient, to densify the first oxide layer and to dope the first oxide layer at its surface and for a portion thereinto near its surface with a gettering agent; oxidizing the semiconductor body a second time, under an oxidizing ambient, to form a second oxide layer upon the first oxide layer, subsequent to the first annealing step; and annealing the semiconductor body a second time, under an NO ambient, thereby forming a third oxide layer upon the second oxide layer, the third oxide layer containing a concentration of nitrogen; wherein the first, second, and third oxide layers together form a high quality oxide.
Claim 18
Dependent Claim
179 words
In an integrated circuit fabrication process suitable for EEPROM devices, a method of forming a high-quality tunnel oxide upon a surface region of semiconductor body over a heavily-doped N+ layer therein, comprising the steps of: forming a heavily-doped N+ layer in the semiconductor body; oxidizing the semiconductor body a first time, under an oxidizing ambient, subsequent to the N+ layer forming step, to form an oxide upon a surface region of the semiconductor body over the heavily-doped N+ layer; annealing the semiconductor body a first time, under a gettering ambient, subsequent to the first oxidizing step, to densify the oxide and to dope the oxide at its surface and for a portion thereinto near its surface with a gettering agent; oxidizing the semiconductor body a second time, under an oxidizing ambient, subsequent to the first annealing step, to thicken the oxide: and annealing the semiconductor body for a second time, under an ambient consisting essentially of NO. subsequent to the second oxidizing step, thereby further thickening the oxide and forming a surface layer therein containing a concentration of nitrogen.
Claim 19
Dependent Claim
19 words
A method as in claim 17 or claim 18, wherein the second annealing step comprises a RTA annealing step.
Claim 20
Dependent Claim
18 words
A method as in claim 19, wherein the first annealing step is performed under an HC1/Ar ambient environment.
Claim 21
Dependent Claim
21 words
A method as in claim 20, wherein the first annealing step is performed at a temperature of about 850 degree(s) C.
Claim 22
Dependent Claim
33 words
A method as in claim 19, further comprising the step of heavily doping a portion of the semiconductor body under the surface region of the semiconductor body prior to the first oxidizing step.
Claim 23
Dependent Claim
107 words
A method as in claim 22, further comprising, subsequent to the second oxidizing step and prior to the second annealing step, the steps of: annealing the semiconductor body a third time, under a gettering ambient, to densify the second oxide layer and to dope the second oxide layer at its surface and for a portion thereinto near its surface with a gettering agent; and oxidizing the semiconductor body a third time, under an oxidizing ambient, subsequent to the third annealing step, to form a fourth oxide layer upon the second oxide layer; wherein the first, second, third, and fourth oxide layers together form a high quality oxide.
Claim 24
Dependent Claim
184 words
In an integrated circuit fabrication process suitable for EEPROM devices, a method for forming a tunnel oxide upon a first surface region of a semiconductor body over a heavily-doped N+ layer, and further for forming a gate oxide, of greater thickness than the tunnel oxide, upon a second surface region of the semiconductor body, comprising the steps of: growing a first oxide upon the first surface region of the semiconductor body over the heavily-doped N+ layer, and upon the second surface region of the semiconductor body; removing a region of the first oxide, to expose a surface of the semiconductor body over the heavily-doped N+ layer, and leaving a remaining region of the first oxide; oxidizing the semiconductor body to form a tunnel oxide on the exposed surface of the semiconductor body while re-oxidizing the remaining region of the first oxide to form the gate oxide; and annealing the semiconductor body a first time, under an ambient atmosphere consisting essentially of NO, to further thicken the tunnel oxide and gate oxide and to form a surface layer each therein containing a concentration of nitrogen.
Claim 25
Dependent Claim
96 words
A method as in claim 24, wherein the oxidizing step comprises the steps of: oxidizing the semiconductor body a first time, under an oxidizing ambient, to form an oxide upon the surface region; annealing the semiconductor body a second time, under a gettering ambient, subsequent to the first oxidizing step, to densify the oxide and to dope the oxide at its surface and for a portion thereinto near its surface with a gettering agent; and oxidizing the semiconductor body a second time, under an oxidizing ambient, subsequent to the second annealing step, to thicken the oxide.
Claim 26
Dependent Claim
16 words
A method as in claim 24, wherein the first annealing step comprises an RTA annealing step.
Claim 27
Dependent Claim
18 words
A method as in claim 26, wherein the second annealing step is performed under an HCl/Ar ambient environment.
Claim 28
Dependent Claim
21 words
A method as in claim 27, wherein the second annealing step is performed at a temperature of about 850 degree(s) C.
Claim 29
Dependent Claim
26 words
A method as in claim 19, 21 or 28, wherein the first and second oxidizing steps are performed at a temperature of about 850 degree(s) C.
Claim 30
Dependent Claim
88 words
A method as in claim 29, when dependent on claim 21, further comprising, subsequent to the second oxidizing step and prior to the second annealing step, the steps of: annealing the semiconductor body a third time, under a gettering ambient, to further densify the oxide and to dope the oxide at its surface and for a portion thereinto near its surface with a gettering agent; and oxidizing the semiconductor body a third time, under an oxidizing ambient, subsequent to the third annealing step, to further thicken the oxide.
Claim 31
Independent Claim
60 words
A method of forming an oxide layer of an integrated circuit comprising the steps of: receiving a gas comprising NO into a chamber containing at least one semiconductor structure, the semiconductor structure comprising a substrate and the oxide layer; and exposing the oxide layer to the gas, thereby forming a region in the oxide layer having a concentration of nitrogen.
Claim 32
Dependent Claim
43 words
The method as recited in claim 31 wherein the chamber is one used in a rapid thermal anneal (RTA) system; a standard diffusion tube; one used in a chemical vapour deposition process; or one used in a plasma enhanced chemical vapour deposition process.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.