EP0689141A2
Expired / Lapsed
EP
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Interrupt-based hardware support for profiling system performance
Assignee: AT&T Inc
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Filing: 1995-05-24
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Granted: —
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Expires: 2015-05-24
Abstract
Abstract In order to get empirical data on memory behaviour to guide system optimisation, a system and method for profiling computer systems is presented. By augmenting a cache miss counter with a compare register and an interrupt line, the processor is interrupted when the counter matches the compare value, and the state of the processor is sampled. This can happen at a predetermined number of cache misses or cache stall cycles. Using these sampled data, a cache miss profile can be developed that associates cache misses with specific processes, procedures, procedure call stacks, or even user defined aspects of the system. Also, the system is able to provide assistance in isolating performance bottlenecks and guiding optimisation of architectures, operating systems, compilers and applications.
Inventors
- 👤 Prathima Agrawal
- 👤 John Andrew Trotter
- 👤 Aaron Jay Goldberg
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 13:57
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/30; G06F11/34; G06F11/3466; G06F11/348; G06F11/3409; G06F11/3447; G06F2201/00; G06F2201/805; G06F2201/86; G06F2201/88; G06F2201/885
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
120 words
A system for profiling the behavior of memory systems in a processor, comprising: an event detector configured to generate a detection signal upon an occurrence of a predetermined event; a counter, coupled to said event detector, configured to receive and count occurrences of said detection signal received from said event detector, said counter further configured to generate a pulse signal when a predetermined count value of said detection signal occurrences is reached; an interrupt generator, coupled to said counter, configured to generate a profiling interrupt signal upon receipt of said pulse signal; and an interrupt handler residing in the processor, configured to record a state of the processor upon receipt of said profiling interrupt signal generated by said interrupt generator.
Claim 2
Dependent Claim
22 words
The system of claim 1, wherein said event detector, said interrupt generator, and said counter are implemented in one or more PALs.
Claim 3
Dependent Claim
25 words
The system of claim 1, wherein said counter is a down counter, said down counter generating said pulse signal when said count value is zero.
Claim 4
Dependent Claim
22 words
The system of claim 1, wherein said counter is a loadable counter, said loadable counter configured to receive said predetermined count value.
Claim 5
Dependent Claim
16 words
The system of claim 1, wherein the memory system resides in a Sun SPARC 10/41 workstation.
Claim 6
Dependent Claim
32 words
The system of claim 1, wherein said event decoder monitors a memory bus and outputs said detection signal when a main memory read signal is received to detect second level cache misses.
Claim 7
Dependent Claim
24 words
The system of claim 1, wherein said counter comprises a reset input configured to enable an external reset signal to reset said down counter.
Claim 8
Dependent Claim
24 words
The system of claim 1, wherein said counter comprises an enable input configured to enable an external enable signal to enable said down counter.
Claim 9
Dependent Claim
50 words
The system of claim 1, wherein said event detector detects data cache stall time, said counter counting a number of clock cycles during which said event detector receives a cache stall signal, said cache stall signal having a predetermined value when the processor pipeline is waiting on a data cache.
Claim 10
Dependent Claim
18 words
The system of claim 1, wherein said event decoder detects primary cache misses and second level cache misses.
Claim 11
Dependent Claim
26 words
The system of claim 1, wherein said counter further comprises an enable input, said counter configured to count said event when said enable bit is set.
Claim 12
Dependent Claim
202 words
A performance monitor system for simultaneous profiling of multiple conditions in a processor memory system, comprising: a plurality of condition detectors, each of said plurality of condition detectors configured to monitor a predetermined condition and to generate a detection signal upon an occurrence of said predetermined condition; a plurality of counters, each of said plurality of counters coupled to a respective one of said plurality of condition detectors, for receiving said detection signal and for generating a count signal indicating the number of said detection signals received; a plurality of loadable compare registers, each of said plurality of loadable compare registers coupled to a respective one of said plurality of counters, configured to receive said count signal from said respective counter and for comparing said count signal to a predetermined value loaded in said each of said plurality of compare registers; an interrupt generator, coupled to each of said plurality of comparators, configured to generate a profiling interrupt signal based upon a predetermined relationship between said pulse signals received from said plurality of comparators; and an interrupt handler, residing in the processor, configured to record a state of the processor upon receipt of said profiling interrupt signal generated by said interrupt generator.
Claim 13
Dependent Claim
17 words
The system of claim 12, wherein the performance monitor is implemented in a field programmable gate array.
Claim 14
Dependent Claim
36 words
The system of claim 12, wherein each of said plurality of counters comprises an enable input, said enable input enabling each of said plurality of counters to count said event when said enable bit is set.
Claim 15
Dependent Claim
132 words
A network monitoring system for monitoring the interactions between the cooperating processors in a distributed system having multiple processors connected by a communication network, comprising: an event detector configured to generate a detection signal upon an occurrence of a predetermined event; a counter, coupled to said event detector, configured to receive and count occurrences of said detection signal received from said event detector, said counter further configured to generate a pulse signal when a predetermined count value of said detection signal occurrences is reached; an interrupt generator, coupled to said counter, configured to generate a profiling interrupt signal upon receipt of said pulse signal; and an interrupt handler residing in the processor, configured to record a state of the processor upon receipt of said profiling interrupt signal generated by said interrupt generator.
Claim 16
Dependent Claim
11 words
The system of claim 15, wherein said multiple processors are workstations.
Claim 17
Dependent Claim
18 words
The system of claim 15, wherein the performance monitor monitors the distribution of wait times on the network.
Claim 18
Dependent Claim
24 words
The system of claim 15, wherein said predetermined value is a random number, thereby causing the system to sample the network at random intervals.
References Cited (Backward Citations)
No citation records indexed.
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