Cache memory having lockable entries

Claim 2

A cache memory according to claim 1, wherein said control circuit controls lock bits and replace bits in blocks such that all blocks in the same set are not simultaneously locked.

Claim 3

A cache memory according to claim 1, wherein said control circuit controls said lock information to have the same state transition in either one of read hit, write hit, and refill hit at the time of cache access hit.

Claim 4

A cache memory employing a set associative scheme or a full associative scheme, comprising: a memory section including: a replace information storage area for storing replace information designating block data to be replaced next among a plurality block data in the same set; a lock information storage area for storing lock information designating that replacement of block data in the same set is inhibited to be held in said cache memory; a valid information storage area for storing valid information indicating whether said block data in each block is valid or not; a block address storage area for storing block addresses of block data stored in each block; and a block data storage area for storing block data of each block; a comparator for comparing said block address stored in said block address storage area of said block wherein said valid information stored in said valid information storage area of said memory section is valid with said block address input from external devices when cache access is effected, and outputs a hit signal when both address coincide with each other; and a cache control circuit for controlling update of said replace information, said lock information and said valid information such that all blocks in the same set are not simultaneously locked, on the basis of input of said replace information stored in said replace information storage area of accessed set, said lock information stored in said lock information storage area, said hit signal output from said comparator, and autolock information designating that said block data is locked in said cache memory when said cache access is effected.

Claim 5

A cache memory according to claim 4, wherein said cache memory is formed of a cache memory employing a 2-way set associative scheme, said replace information storage area of said memory section stores 1 bit information designating whether a way is to be next replaced or not in every set, said lock information storage area of said memory section stores 1 bit information designating whether either way is locked or not in every set, and said cache control circuit controls said replace information stored in said replace information storage area not to be updated in case block data in either way is locked.

Claim 6

A cache memory according to claim 4, wherein said lock information storage area of said memory section stores 1 bit information designating whether a block is locked or not in every block, said cache control circuit controls update of said lock information stored in said lock information storage area such that all block data in the same set are not simultaneously locked.

Claim 7

A cache memory according to claim 4, wherein said control circuit controls said lock information to have the same state transition in either one of read hit, write hit, and refill hit at the time of cache access hit.

Claim 8

A cache memory employing a set associative scheme or a full associative scheme for managing a plurality of blocks as one set, comprising: a tag address storage area for storing tag addresses; a data storage area for storing block data corresponding to said tag addresses; a lock information storage area for storing lock information indicating whether replace of each block is inhibited or not; and a control circuit for managing said lock information in a block in accordance with states of an autolock signal and a lock bit signal at the time of access hit such that all blocks in the same set are not simultaneously locked.

Claim 9

A cache memory according to claim 8, wherein said control circuit controls said lock information to have the same state transition in either one of read hit, write hit, and refill hit at the time of cache access hit.