EP0685798A2
Expired / Lapsed
EP
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Interrupt controllers in symmetrical multiprocessing systems
Assignee: Advanced Micro Devices Inc
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Filing: 1995-05-17
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Granted: —
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Expires: 2015-05-17
Abstract
Abstract A symmetrical multiprocessing system is provided that includes centralized interrupt control unit. The interrupt control unit is coupled to a plurality of processing units and to a plurality of interrupt sources. The interrupt control unit advantageously allows for the expansion of each interrupt pin by setting the interrupt control unit in a cascade mode. Furthermore, the central control unit is responsive to specialized interrupt cycles which allows I/O devices and/or bus bridge devices to initiate of an interrupt without requiring a dedicated interrupt line. The central interrupt control unit further allows each interrupt to be prioritized independently of its associated vector ID, and prevents the occurrence of spurious interrupts by providing a programmable latency timer which causes the central interrupt control unit to delay its response to End Of Interrupt (EOI) instructions. An auto-chaining technique is further implemented by the central interrupt control unit to sequentially provide broadcast interrupts to various processing units based on their current task priority values. Finally, the central interrupt control unit further handles system management interrupts (SMIs) from sources such as power management units and ensures proper system operation even if the requested system management function affects operations being carried by other processing units.
Inventors
- 👤 Douglas Gephardt
- 👤 James Macdonald
- 👤 Rodney Schmidt
- 👤 Rupaka Mahalingaiah
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 19:46
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/17; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06F13/26
Claims Analysis
Total Claims: 55
Claim 1
Independent Claim
105 words
A symmetrical multiprocessing system comprising: a plurality of processing units; a CPU local bus coupled to each of said processing units; a first I/O bus; a first bus bridge coupled between said CPU local bus and said I/O bus for providing an interface between said CPU local bus and said I/O bus; a plurality of I/O devices coupled to said I/O bus; and a programmable central interrupt control unit coupled to said plurality of I/O devices, wherein said central interrupt control unit is configured to receive interrupt signals from said plurality of I/O devices and to selectively provide corresponding interrupt signals to said processing units.
Claim 2
Dependent Claim
105 words
A symmetrical multiprocessing system comprising: a plurality of processing units; a CPU local bus coupled to each of said processing units; a first I/O bus; a first bus bridge coupled between said CPU local bus and said I/O bus for providing an interface between said CPU local bus and said I/O bus; a plurality of I/O devices coupled to said I/O bus; and a programmable central interrupt control unit coupled to said plurality of I/O devices, wherein said central interrupt control unit is configured to receive interrupt signals from said plurality of I/O devices and to selectively provide corresponding interrupt signals to said processing units.
Claim 3
Dependent Claim
23 words
The symmetrical multiprocessing system as recited in claim 1 wherein said central interrupt control unit is embodied on a single integrated circuit chip
Claim 4
Dependent Claim
42 words
The symmetrical multiprocessing system as recited in claim 1 further comprising an interrupt controller coupled between an I/O device and said I/O bus, wherein said central interrupt control unit is further configured to receive an interrupt signal generated by said interrupt controller.
Claim 5
Dependent Claim
72 words
The symmetrical multiprocessing system as recited in claim 1 further comprising: a second I/O bus coupled to an I/O device; and a second bus bridge coupled between said first I/O bus and said second I/O bus, said second bus bridge being capable of providing an interface between said first and second I/O buses and further being capable of generating an interrupt cycle in response to an interrupt signal from said I/O device.
Claim 6
Dependent Claim
37 words
The symmetrical multiprocessing system as recited in claim 3 wherein said central interrupt control unit includes an interrupt cycle decoder, said interrupt cycle decoder being capable of detecting an interrupt cycle generated by said second bus bridge.
Claim 7
Dependent Claim
102 words
An interrupt control unit for a symmetrical multiprocessing system comprising: a plurality of interrupt input pins; an interrupt channel coupled to each of said interrupt input pins, wherein each interrupt channel includes a control register for storing configuration information indicative of an incoming interrupt signal; a central controller coupled to each of said interrupt channels; and a plurality of CPU channels each coupled to said central controller, wherein each of said CPU channels is dedicated to a separate processing unit, and wherein each of said CPU channels includes a configuration register indicative of a task priority level of an associated processing unit.
Claim 8
Dependent Claim
102 words
An interrupt control unit for a symmetrical multiprocessing system comprising: a plurality of interrupt input pins; an interrupt channel coupled to each of said interrupt input pins, wherein each interrupt channel includes a control register for storing configuration information indicative of an incoming interrupt signal; a central controller coupled to each of said interrupt channels; and a plurality of CPU channels each coupled to said central controller, wherein each of said CPU channels is dedicated to a separate processing unit, and wherein each of said CPU channels includes a configuration register indicative of a task priority level of an associated processing unit.
Claim 9
Dependent Claim
28 words
The interrupt control unit as recited in Claim 6 wherein said central controller is capable of selectively providing a given interrupt signal to one of said CPU channels.
Claim 10
Dependent Claim
105 words
The interrupt control unit as recited in claim 7, further comprising: an I/O interrupt controller coupled to said central controller, said I/O interrupt controller including said plurality of interrupt input terminals; an I/O bus interface unit coupled between said central controller and said I/O bus and capable of providing an interface between said central controller and said I/O bus; and a processor interrupt generator coupled to said central controller, said processor interrupt generator including said plurality of CPU channels and being capable of selectively providing a given decoded prioritized interrupt signal to one or more of said processing units through said plurality of CPU channels.
Claim 11
Dependent Claim
66 words
The interrupt control unit as recited in claim 7, further comprising a CPU bus interface unit coupled between a CPU local bus and said central controller and capable of providing an interface between said CPU local bus and said central controller, wherein said interrupt controller is capable of receiving interrupt signals from a plurality of processing units and distributing said interrupt signals to designated processing units.
Claim 12
Dependent Claim
117 words
A symmetrical multiprocessing system comprising: a plurality of processing units; a plurality of I/O devices; a central interrupt control unit capable of receiving interrupt signals from said plurality of I/O devices and distributing said interrupt signals to designated processing units, wherein said central interrupt control unit includes a plurality of interrupt input terminals; and a remote interrupt handler coupled to said plurality of I/O devices and to one of said interrupt terminals of said central interrupt control unit, wherein said remote interrupt handler is capable of transmitting a serial signal to said interrupt terminal of said central interrupt control unit indicative of a status of a plurality of interrupt signals provided from said plurality of I/O devices.
Claim 13
Dependent Claim
117 words
A symmetrical multiprocessing system comprising: a plurality of processing units; a plurality of I/O devices; a central interrupt control unit capable of receiving interrupt signals from said plurality of I/O devices and distributing said interrupt signals to designated processing units, wherein said central interrupt control unit includes a plurality of interrupt input terminals; and a remote interrupt handler coupled to said plurality of I/O devices and to one of said interrupt terminals of said central interrupt control unit, wherein said remote interrupt handler is capable of transmitting a serial signal to said interrupt terminal of said central interrupt control unit indicative of a status of a plurality of interrupt signals provided from said plurality of I/O devices.
Claim 14
Dependent Claim
39 words
The symmetrical multiprocessing system as recited in claim 10 wherein said remote interrupt handler includes an interrupt data encoder capable of encoding information indicative of a transition in one of said interrupt signals from said plurality of I/O devices.
Claim 15
Dependent Claim
128 words
The symmetrical multiprocessing system as recited in claim 11, wherein said remote interrupt handler further includes: an interrupt detect circuit coupled to said interrupt data encoder and capable of monitoring said plurality of I/O devices and of receiving a parallel input indicative of said interrupt signals from said plurality of I/O devices; a shift register coupled to said interrupt data encoder and capable of providing a synchronizing shift clock to facilitate the transmission of said serial signal to said interrupt terminal of said central interrupt control unit; and an interrupt data encoder coupled between said interrupt detect circuit and said shift register, said interrupt data encoder being capable of generating an encoded serial signal indicative of a status of an interrupt signal provided by said interrupt detect circuit.
Claim 16
Dependent Claim
91 words
The symmetrical multiprocessing system as recited in claim 11 further including an interrupt input processor coupled to said remote interrupt handler, said interrupt input processor including: a shifter control coupled to said remote interrupt handler and capable of receiving a serial signal indicative of a status of a plurality of interrupt signals provided from said plurality of I/O devices; and a serial decode circuit coupled to said shifter control and capable of decoding said serial signal and providing an interrupt signal to a central controller of said central interrupt control unit;
Claim 17
Dependent Claim
62 words
The symmetrical multiprocessing system as recited in claim 13 wherein said interrupt input processor further includes a control unit coupled to said shifter control, said serial decode circuit and a registers unit, wherein said control unit is capable of receiving a control signal indicative of a mode of interrupt handling and of selectively enabling said shifter control and said serial decode circuit.
Claim 18
Dependent Claim
27 words
The symmetrical multiprocessing system as recited in claim 14 wherein said control unit is responsive to a setting of a plurality of bits in said registers unit.
Claim 19
Independent Claim
72 words
A method for cascading an interrupt terminal of an interrupt controller comprising the steps of: receiving a plurality of interrupt signals at a remote interrupt handler; transmitting a serial signal indicative of said interrupt signals from said remote interrupt handler to said interrupt terminal of said interrupt controller; decoding said serial signal within said interrupt controller; and providing a corresponding interrupt signal to a processing unit in accordance with said serial signal.
Claim 20
Independent Claim
72 words
A method for cascading an interrupt terminal of an interrupt controller comprising the steps of: receiving a plurality of interrupt signals at a remote interrupt handler; transmitting a serial signal indicative of said interrupt signals from said remote interrupt handler to said interrupt terminal of said interrupt controller; decoding said serial signal within said interrupt controller; and providing a corresponding interrupt signal to a processing unit in accordance with said serial signal.
Claim 21
Dependent Claim
34 words
The method for cascading an interrupt terminal of an interrupt controller as recited in claim 16 further comprising the step of encoding a serial signal indicating a state and source of an interrupt signal.
Claim 22
Dependent Claim
84 words
An interrupt controller for a symmetrical multiprocessing system comprising: a plurality of interrupt channels for receiving interrupt signals from I/O devices; a central controller coupled to said interrupt channels; a plurality of CPU channels coupled to said central controller for providing selected interrupt signals to selected processing units; and an interrupt cycle decoder coupled to at least one of said interrupt channels and capable of providing an interrupt signal to said interrupt channel in response to an interrupt cycle executed on an I/O bus.
Claim 23
Dependent Claim
84 words
An interrupt controller for a symmetrical multiprocessing system comprising: a plurality of interrupt channels for receiving interrupt signals from I/O devices; a central controller coupled to said interrupt channels; a plurality of CPU channels coupled to said central controller for providing selected interrupt signals to selected processing units; and an interrupt cycle decoder coupled to at least one of said interrupt channels and capable of providing an interrupt signal to said interrupt channel in response to an interrupt cycle executed on an I/O bus.
Claim 24
Dependent Claim
27 words
The interrupt controller as recited in Claim 18 wherein a control register of said interrupt channel includes at least one bit for enabling said interrupt cycle decoder.
Claim 25
Dependent Claim
33 words
20 The interrupt controller for a symmetrical multiprocessing system as recited in claim 18 wherein said interrupt cycle on said I/O bus is executed by a bus bridge coupled to said I/O bus.
Claim 26
Dependent Claim
32 words
The interrupt controller for a symmetrical multiprocessing system as recited in claim 18 wherein said interrupt cycle on said I/O bus is executed by an interrupt controller coupled to said I/O bus.
Claim 27
Dependent Claim
46 words
The interrupt controller for a symmetrical multiprocessing system as recited in claim 18 wherein said I/O bus is a PCI standard configuration bus, and said interrupt cycle is defined by a pre-specified coding of a plurality of cycle definition bits of said PCI standard configuration bus.
Claim 28
Dependent Claim
34 words
The interrupt controller for a symmetrical multiprocessing system as recited in claim 18 wherein said interrupt cycle is defined as a cycle to a predetermined address in memory space of said symmetrical multiprocessing system.
Claim 29
Dependent Claim
34 words
The interrupt controller for a symmetrical multiprocessing system as recited in claim 18 wherein said interrupt cycle is defined as a cycle to a predetermined address in I/O space of said symmetrical multiprocessing system.
Claim 30
Independent Claim
81 words
A method for initiating a processor interrupt signal within a symmetrical multiprocessing system comprising the steps of: asserting a local interrupt signal within an I/O device; providing said local interrupt signal to a bus bridge; executing an interrupt cycle on a bus coupled to said bus bridge in response to said local interrupt signal; decoding said interrupt cycle on said bus within an interrupt control unit; and providing an interrupt signal to a processing unit in response to said interrupt cycle.
Claim 31
Independent Claim
81 words
A method for initiating a processor interrupt signal within a symmetrical multiprocessing system comprising the steps of: asserting a local interrupt signal within an I/O device; providing said local interrupt signal to a bus bridge; executing an interrupt cycle on a bus coupled to said bus bridge in response to said local interrupt signal; decoding said interrupt cycle on said bus within an interrupt control unit; and providing an interrupt signal to a processing unit in response to said interrupt cycle.
Claim 32
Dependent Claim
132 words
An interrupt controller comprising: a plurality of interrupt input terminals configured to receive a plurality of interrupt signals; a central controller coupled to said input terminals for prioritizing said interrupt signals and for providing said interrupt signals to at least one processing unit; a status register coupled to said central controller for storing information indicative of whether a particular interrupt signal is idle, wherein said central controller controls the status of said status register according to interrupt signals dispatched to said processing unit and an End Of Interrupt command executed by said processing unit; and a programmable latency timer coupled to said central controller, wherein a value within said programmable latency timer controls a time at which said central controller updates said status register in response to an End Of Interrupt command.
Claim 33
Dependent Claim
132 words
An interrupt controller comprising: a plurality of interrupt input terminals configured to receive a plurality of interrupt signals; a central controller coupled to said input terminals for prioritizing said interrupt signals and for providing said interrupt signals to at least one processing unit; a status register coupled to said central controller for storing information indicative of whether a particular interrupt signal is idle, wherein said central controller controls the status of said status register according to interrupt signals dispatched to said processing unit and an End Of Interrupt command executed by said processing unit; and a programmable latency timer coupled to said central controller, wherein a value within said programmable latency timer controls a time at which said central controller updates said status register in response to an End Of Interrupt command.
Claim 34
Dependent Claim
18 words
The interrupt controller as recited in Claim 26 wherein said latency timer is programmable through an I/O bus.
Claim 35
Dependent Claim
29 words
The interrupt controller as recited in claim 26 wherein said central controller resets a particular interrupt to an idle state a predetermined time after said End Of Interrupt command.
Claim 36
Dependent Claim
56 words
The interrupt controller as recited in claim 26 further including an I/O interrupt controller coupled between said plurality of interrupt input terminals and said central controller, said I/O interrupt controller being capable of monitoring a status of a plurality of interrupt signals and selectively responding to an assertion of any of said plurality of interrupt signals.
Claim 37
Dependent Claim
32 words
The interrupt controller as recited in claim 29 wherein said I/O interrupt controller monitors the status of an interrupt if said status register indicates that said interrupt is in an idle state.
Claim 38
Dependent Claim
50 words
The interrupt controller as recited in claim 26 further including a processor interrupt generator coupled to said central controller, said processor interrupt generator including a plurality of interrupt output terminals coupled to a plurality of processing units and being capable of dispatching interrupt signals to said plurality of processing units.
Claim 39
Dependent Claim
49 words
The interrupt controller as recited in claim 26 further including a decoder coupled between an I/O bus and said programmable latency timer, said decoder being capable of detecting an End Of Interrupt command and of enabling said programmable latency timer upon the occurrence of said End Of Interrupt command.
Claim 40
Independent Claim
89 words
A method for preventing spurious interrupts within a computer system comprising the steps of: receiving an interrupt signal within an interrupt controller; dispatching said interrupt signal to a processing unit; updating a status register to indicate that said interrupt signal is being serviced; receiving an End Of Interrupt command from said processing unit when said processing unit has completed processing said interrupt signal; waiting for a programmable period of time; and updating said status register to indicate that said interrupt signal is idle following said programmable period of time.
Claim 41
Independent Claim
89 words
A method for preventing spurious interrupts within a computer system comprising the steps of: receiving an interrupt signal within an interrupt controller; dispatching said interrupt signal to a processing unit; updating a status register to indicate that said interrupt signal is being serviced; receiving an End Of Interrupt command from said processing unit when said processing unit has completed processing said interrupt signal; waiting for a programmable period of time; and updating said status register to indicate that said interrupt signal is idle following said programmable period of time.
Claim 42
Dependent Claim
18 words
The method as recited in Claim 33 comprising the further step of programming said programmable period of time.
Claim 43
Independent Claim
71 words
A method of broadcasting an interrupt signal within a symmetrical multiprocessing system including a plurality of processing units comprising the steps of: receiving said interrupt signal at a central control unit; determining relative task priorities of said plurality of processing units; interrupting a designated processing unit having the lowest current task priority; waiting for said designated processing unit to complete service of said interrupt; and interrupting another of said processing units.
Claim 44
Independent Claim
71 words
A method of broadcasting an interrupt signal within a symmetrical multiprocessing system including a plurality of processing units comprising the steps of: receiving said interrupt signal at a central control unit; determining relative task priorities of said plurality of processing units; interrupting a designated processing unit having the lowest current task priority; waiting for said designated processing unit to complete service of said interrupt; and interrupting another of said processing units.
Claim 45
Dependent Claim
27 words
The method as recited in Claim 35 wherein the additional processing unit that is interrupted has the lowest current task priority relative to the remaining processing units.
Claim 46
Dependent Claim
43 words
The methcd of broadcasting an interrupt signal within a symmetrical multiprocessing system as recited in claim 35 wherein the step of determining the task priorities of said plurality of processing units is performed by reading a task priority register within a CPU channel.
Claim 47
Dependent Claim
36 words
The method of broadcasting an interrupt signal within a symmetrical multiprocessing system as recited in claim 35 wherein said designated processing unit acknowledges completion of servicing said interrupt signal by asserting an End Of interrupt command.
Claim 48
Dependent Claim
45 words
The method of broadcasting an interrupt signal within a symmetrical multiprocessing system as recited in claim 38 further including the steps of: determining if all of a designated group of said processors have serviced said interrupt signal; and setting said interrupt to an idle state.
Claim 49
Dependent Claim
37 words
The method of broadcasting an interrupt signal within a symmetrical multiprocessing system as recited in claim 39 further including the step of waiting a predetermined period of time after the receipt of said End Of Interrupt command.
Claim 50
Dependent Claim
108 words
An interrupt controller for a symmetrical multiprocessing system comprising: at least one interrupt channel for receiving an interrupt signal; a plurality of CPU channels for distributing selected interrupt signals to dedicated processing units; and a central controller coupled to said interrupt channel and to said CPU channels, wherein said central controller is capable of determining a designated processing unit having a lowest task priority level and of providing said interrupt signal to said designated processing unit, and is subsequently capable of providing said interrupt signal to a subsequent processing unit having a higher associated task priority after said designated processing unit completes its service of said interrupt signal.
Claim 51
Dependent Claim
108 words
An interrupt controller for a symmetrical multiprocessing system comprising: at least one interrupt channel for receiving an interrupt signal; a plurality of CPU channels for distributing selected interrupt signals to dedicated processing units; and a central controller coupled to said interrupt channel and to said CPU channels, wherein said central controller is capable of determining a designated processing unit having a lowest task priority level and of providing said interrupt signal to said designated processing unit, and is subsequently capable of providing said interrupt signal to a subsequent processing unit having a higher associated task priority after said designated processing unit completes its service of said interrupt signal.
Claim 52
Dependent Claim
31 words
The interrupt controller for a symmetrical multiprocessing system as recited in claim 41 wherein said subsequent processing unit has the lowest task priority level of a remaining group of processing units.
Claim 53
Dependent Claim
38 words
The interrupt controller for a symmetrical multiprocessing system as recited in claim 41 wherein said plurality of CPU channels each include a current task priority register for storing the current task priority level of an associated processing unit.
Claim 54
Dependent Claim
32 words
The interrupt controller for a symmetrical multiprocessing system as recited in claim 41 wherein each of said plurality of CPU channels contain a register indicative of an activity state of an interrupt.
Claim 55
Dependent Claim
45 words
The interrupt controller for a symmetrical multiprocessing system as recited in claim 44 wherein said central controller is further capable of determining when all processing units have received and serviced said interrupt and of clearing said register indicative of an activity state of said interrupt.
References Cited (Backward Citations)
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