EP0681373A2
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EP
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Convolutional interleaver with reduced memory requirements and address generator therefor
Assignee: Arris Technology Inc
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Filing: 1995-05-03
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Granted: —
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Expires: 2015-05-03
Abstract
Abstract A convolutional interleaver and addressing scheme are provided. Up to B consecutive symbols containing errors can be interleaved such that they are separated from each other by at least N intervening symbols. Memory, such as RAM, is configured to provide (B-1) cells of increasing size for storing symbols from a data stream. A first one of the cells (CELL 1) has M storage locations adapted to store M symbols. Each successive one of the cells (CELL 2; CELL 3) has M more storage locations than the immediately preceding cell for storing M more symbols than the immediately preceding cell, where M=N/B . The cells are successively addressed to write a next symbol from the stream into a next write symbol location in a currently addressed cell and to read a symbol from the location of the currently addressed cell immediately following the next write symbol location. The locations are accessed in a first revolving manner such that the last location in a cell is followed by the first location in that cell. The cells are addressed in a second revolving manner such that the (B-1)th cell is followed by the first cell, or vice versa. An intervening transfer stage can be provided within the RAM between the (B-1)th cell and the first cell to directly transfer the next symbol to the interleaver output. Each consecutive symbol from the stream is written into a next consecutive one of the cells. A deinterleaver is provided having the same structure.
Inventors
- 👤 Zheng Huang
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 20:19
CPC Classifications
H; H03; H03M; H03M13/00; H03M13/27; H03M13/2782; H03M13/2732; H03M13/276
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
211 words
A convolutional interleaver for interleaving a stream of symbols to separate up to B consecutive symbols containing errors such that said error containing symbols are separated from each other by at least N intervening symbols, comprising: memory means configured to provide (B-1) cells of increasing size for storing symbols from said stream, a first one of said cells having M storage locations adapted to store M symbols and each successive one of said cells having M more storage locations than an immediately preceding cell for storing M more symbols than said immediately preceding cell, where M = N/B ; means for successively addressing said cells to write a next symbol from said stream into a next write symbol location in a currently addressed cell and to read a symbol from the location of the currently addressed cell immediately following said next write symbol location, wherein: said locations are accessed in a first revolving manner such that the last location in a cell is followed by the first location in that cell, said cells are addressed in a second revolving manner such that the (B-1)th cell is followed by the first cell or vice versa, and each consecutive symbol from said stream is written into a next consecutive one of said cells.
Claim 2
Dependent Claim
104 words
An interleaver in accordance with claim 1 wherein said addressing means comprise: (B-1) accumulators, each associated with a different one of said (B-1) cells; means for initializing each of said accumulators with a starting location in the cell associated therewith; means for incrementing the accumulators to address a next location in the cell associated therewith after a symbol is written into that cell, said incrementing means adapted to access the storage locations in the cell in said first revolving manner; and means for sequentially coupling said accumulators to an address port of said memory means to address said cells in said second revolving manner.
Claim 3
Dependent Claim
103 words
An interleaver in accordance with claim 2 wherein said memory means comprise a random access memory having a write control and a read control in addition to said address port, said interleaver further comprising: control means for actuating said write control when an accumulator is first coupled to said address port to enable the next symbol in said data stream to be written into the cell and cell location pointed to by the accumulator, and for actuating said read control when the accumulator has been incremented to the next cell location to enable a symbol to be read from said next cell location.
Claim 4
Dependent Claim
102 words
An interleaver in accordance with claim 1 wherein said memory means comprise a random access memory having an address port, a write control and a read control, said interleaver further comprising: control means for actuating said write control to enable the next symbol in said data stream to be written into a cell and cell location specified by an address that is input to said address port from said addressing means, and for actuating said read control after said address has been incremented to the immediately following cell location to enable a symbol to be read from said immediately following cell location.
Claim 5
Dependent Claim
59 words
An interleaver in accordance with one of the preceding claims, wherein a transfer stage is provided between said (B-1)th cell and said first cell, and said cells are addressed in said second revolving manner such that the (B-1)th cell is immediately followed by said transfer stage which, in turn, is immediately followed by said first cell, or vice versa.
Claim 6
Dependent Claim
19 words
An interleaver in accordance with claim 5 wherein said transfer stage comprises a storage location of said memory means.
Claim 7
Dependent Claim
182 words
An address generator for a (B,N) convolutional interleaver/deinterleaver, where B is a maximum number of consecutive symbols containing burst errors that can be separated by the interleaver and N is a minimum separation inserted between errors by the interleaver, said address generator comprising: (B-1) accumulators, each associated with a different one of (B-1) interleaver or deinterleaver cells of progressively increasing length; means for initializing each of said accumulators with a starting address specifying a first storage location in the cell associated with the accumulator; means for incrementing each accumulator to a next cell location address after a symbol is written into the cell associated with the accumulator, said next cell location addresses being provided in a first revolving manner such that the first location in a cell is addressed after the last location in that cell; and means for coupling said accumulators to address said cells in a second revolving manner such that the (B-1)th cell is followed by the first cell or vice versa; wherein each consecutive symbol from said stream is written into a next consecutive one of said cells.
Claim 8
Dependent Claim
87 words
An address generator in accordance with claim 7 further comprising: control means for actuating a write control input of said cells when an accumulator is first coupled to address a cell to enable the next symbol in said data stream to be written into the cell and cell location pointed to by the accumulator, and for actuating a read control input of said cells when the accumulator has been incremented to the next cell location to enable a symbol to be read from said next cell location.
Claim 9
Dependent Claim
59 words
An address generator in accordance with claim 7 or 8 wherein a transfer stage is provided between said (B-1)th cell and said first cell, and said cells are addressed in said second revolving manner such that the (B-1)th cell is immediately followed by said transfer stage which, in turn, is immediately followed by said first cell, or vice versa.
Claim 10
Dependent Claim
20 words
An address generator in accordance with claim 9 wherein said transfer stage comprises a storage location of said memory means.
Claim 11
Dependent Claim
207 words
A convolutional deinterleaver for reconstructing sets of B consecutive symbols that are separated from each other in an interleaved data stream by at least N intervening symbols, comprising: memory means configured to provide (B-1) cells of increasing size for storing symbols from said stream, a first one of said cells having M storage locations adapted to store M symbols and each successive one of said cells having M more storage locations than an immediately preceding cell for storing M more symbols than said immediately preceding cell, where M = N/B ; means for successively addressing said cells to write a next symbol from said interleaved data stream into a next write symbol location in a currently addressed cell and to read a symbol from the location of the currently addressed cell immediately following said next write symbol location, wherein: said locations are accessed in a first revolving manner such that the last location in a cell is followed by the first location in that cell, said cells are addressed in a second revolving manner such that the (B-1)th cell is followed by the first cell or vice versa, and each consecutive symbol from said interleaved data stream is written into a next consecutive one of said cells.
Claim 12
Dependent Claim
104 words
A deinterleaver in accordance with claim 11 wherein said addressing means comprise: (B-1) accumulators, each associated with a different one of said (B-1) cells; means for initializing each of said accumulators with a starting location in the cell associated therewith; means for incrementing the accumulators to address a next location in the cell associated therewith after a symbol is written into that cell, said incrementing means adapted to access the storage locations in the cell in said first revolving manner; and means for sequentially coupling said accumulators to an address port of said memory means to address said cells in said second revolving manner.
Claim 13
Dependent Claim
104 words
A deinterleaver in accordance with claim 12 wherein said memory means comprise a random access memory having a write control and a read control in addition to said address port, said deinterleaver further comprising: control means for actuating said write control when an accumulator is first coupled to said address Port to enable the next symbol in said interleaved data stream to be written into the cell and cell location pointed to by the accumulator, and for actuating said read control when the accumulator has been incremented to the next cell location to enable a symbol to be read from said next cell location.
Claim 14
Dependent Claim
103 words
A deinterleaver in accordance with claim 11 wherein said memory means comprise a random access memory having an address port, a write control and a read control, said deinterleaver further comprising: control means for actuating said write control to enable the next symbol in said interleaved data stream to be written into a cell and cell location specified by an address that is input to said address port from said addressing means, and for actuating said read control after said address has been incremented to the immediately following cell location to enable a symbol to be read from said immediately following cell location.
Claim 15
Dependent Claim
60 words
A deinterleaver in accordance with one of claims 11 to 14 wherein a transfer stage is provided between said (B-1)th cell and said first cell, and said cells are addressed in said second revolving manner such that the (B-1)th cell is immediately followed by said transfer stage which, in turn, is immediately followed by said first cell, or vice versa.
Claim 16
Dependent Claim
19 words
A deinterleaver in accordance with claim 15 wherein said transfer stage comprises a storage location of said memory means.
References Cited (Backward Citations)
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