Media error code generation such as for an inverse transport processor

Claim 2

The apparatus set forth in claim 1 characterized in that said memory is operated as a first-in-first-out memory and respective said media error codes are written to memory address locations ahead of associated payloads, and in the absence of said control signal, the media error code is overwritten by first occurring payload data.

Claim 3

The apparatus set forth in claim 1 characterized in that said memory management means includes; a multiplexer having first and second input ports respectively coupled to said source of packeted signal and said source of a media error code, an output port coupled to a data input port of said memory, and a control input terminal; address generating circuitry; delay means coupled to said address counter for delaying address signals by a number of address periods equal to the number of addresses required to load said media error code in said memory; a further multiplexer arranged to pass delayed or undelayed addresses to an address input port of said memory; control circuitry for a) conditioning said multiplexer to coupled said source of a media error code to said memory data input port prior to the occurrence of respective packet payloads, b) conditioning said multiplexer to coupled said source of packeted signal to said memory data input port on the occurrence of respective packet payloads, c) conditioning said further multiplexer to couple nondelayed addresses to said address input port of said memory prior to the occurrence of respective packet payloads, and to continue to couple nondelayed addresses to said address input port on the occurrence of a packet payload and an associated control signal, and d) conditioning said further multiplexer to couple nondelayed addresses to said address input port of said memory for said number of address periods prior to the occurrence of respective packet payloads, then on the occurrence of respective packets and the absence of associated control signals, to couple delayed addresses to said address input port for said number of address periods and then nondelayed addresses.

Claim 4

The apparatus set forth in claim 3 characterized in that said further data which is indicative of the integrity of received signal includes packet header data including a packet continuity count CC, which is a value which is incremented by a predetermined integer for successive packets, and said detection means includes circuitry for detecting whether the continuity count CC of respective packets are in proper sequence, and if not generating said control signal.

Claim 5

The apparatus set forth in claim 4 characterized in that said further data which is indicative of the integrity of received signal further includes in said packet header data, a toggle bit which changes state in predetermined packets, and said detection means includes circuitry for detecting whether the continuity count CC of respective packets are in proper sequence, and whether the toggle bit of successive packets is in the correct state, and if not, generating said control signal.

Claim 6

The apparatus set forth in claim 1 characterized in that said further data which is indicative of the integrity of received signal includes packet header data including a packet continuity count CC, which is a value which is incremented by a predetermined integer for successive packets, and said detection means includes circuitry for detecting whether the continuity count CC of respective packets are in proper sequence, and if not generating said control signal.

Claim 7

The apparatus set forth in claim 6 characterized in that said further data which is indicative of the integrity of received signal further includes in said packet header data, a toggle bit which changes state in predetermined packets and said detection means includes circuitry for detecting whether the continuity count CC of respective packets are in proper sequence, and the toggle bit of successive packets is in the correct state, and if not, generating said control signal.

Claim 8

The apparatus set forth in claim 7 further characterized by apparatus for iniating remedial action in a first mode if only the continuity count CC of a respective packet is not in proper sequence, and iniating remedial action in a second mode if both the continuity count CC of a respective packet is not in proper sequence and the toggle bit is not in the correct state.

Claim 9

In a system for receiving and decompressing packeted data including packets having signal payloads and further data useful for determining the integrity of the received packeted data, said system including memory in which respective payloads are sequentially stored, and wherein media error codes are to be inserted ahead of packet payloads when a data loss is detected, a method for inserting said media error codes characterized by: storing a media error code in said memory in a sequence of memory address locations M to M+N, prior to the occurrence of a packet payload where M and N are integers, and N is the number of address locations required to store the media error code; on the occurrence of a payload, storing said packet payload in said memory in further successive memory locations M+N+1 to M+N+K if a data loss has been detected; and if a data loss has not been detected, on the occurrence of a payload, overwriting said media error code by storing said packet payload in said memory in successive memory locations M to M+K, where K is the number of memory address locations required to store a respective payload.