Packet program component detector

Claim 2

The apparatus set forth in claim 1 characterized in that a respective programmable matched filter comprises: a register having a plurality of storage elements at least equal in number to the number of bits of respective SCID's, having an input port for applying an SCID, a plurality of ordinally numbered output connections respectively associated with each bit of an SCID from least significant bit to most significant bit, a further register, having a plurality of storage elements at least equal in number to the number of bits of respective SCID's, having an input port coupled to said source for loading at least portions of said signal to its storage elements, and having a plurality of ordinally numbered output connections respectively associated with respective storage elements; and logical comparing means arranged for providing a control signal when evey signal exhibited at the ordinally number output connections of the further register are all equivalent to signal exhibited at like ordinally numbered output connections of said register.

Claim 3

The apparatus set forth in claim 2 characterized in that said programmable matched filters include means for disabling said logical comparing means from providing said control signal.

Claim 4

The apparatus set forth in claim 2 characterized in that said logical comparing means includes a plurality of exclusive NOR circuits, ones of which have respective first input connections coupled to respective SCID bit output connections of said register and respective second input connections connected to like ordinally numbered SCID bit output connections of said further register.

Claim 5

The apparatus set forth in claim 4 characterized in that said logical comparing means further includes means for determining when all of said exclusive NOR circuits exhibit a similar output state.

Claim 6

The apparatus set forth in claim 5 characterized in that said logical comparing means includes a further exclusive NOR circuit having a first input connection connected to a predetermined logic value, and a second input connection coupled to a source of selectable logic values, and having an output connected to said means for determining when all of said exclusive NOR circuits exhibit a similar output state, said source of selectable logic values being conditioned to apply a logic level opposite said predetermined logic value to disable said means for determining when all of said exclusive NOR circuits exhibit a similar output state when said programmable matched filters are reprogrammed.

Claim 7

The apparatus set forth in claim 5 characterized in that said source of selectable logic values includes a further storage element in said register.

Claim 8

The apparatus set forth in claim 1 characterized in that signal packets are coupled to respective said signal processors via a decrypting apparatus comprising: a decryptor having an input port coupled to said source, and an output port at which decrypted signal is available, and having a decryption key input port; a plurality of programmable registers having respective input ports for loading decryption keys associated with respective signal components and having respective output ports; a multiplexor having a plurality of input ports respectively coupled to the output ports of said plurality of programmable register, having an output port coupled to said decryption key input port, and a control signal input port coupled to said programmable matched filters for applying decryption keys associated with detected signal components.

Claim 9

The apparatus set forth in claim 8, characterized in that two decryption keys are associated with respective signal components, and respective signal packets include a decryption flag indicating which of said two decryption keys are to be used for a given packet, and the decrypting apparatus further includes a detector responsive to said decryption flag in said signal packets for selecting the one of said two decryption keys to be used with respective signal packets.

Claim 10

The apparatus set forth in claim 1 characterized in that signal packets are coupled to respective said signal processors via a decrypting apparatus comprising: a decryptor having an input port coupled to said source, and an output port at which decrypted signal is available, and having a decryption key input port; a memory having a plurality of address locations for loading respective decryption keys associated with respective signal components, having an output port coupled to said decryption key input port and having an address input port coupled to said programmable matched filter.

Claim 11

The apparatus set forth in claim 1 further characterized by prioritizing apparatus coupled to respective output connections of said plurality of programmable matched filters, for simultaneously passing only a single output control signal from said output connections, and wherein the matched filters are prioritized for which output control signal will be passed if more than one matched filter concurrently provides an output control signal.

Claim 12

In a receiver for processing recorded or transmitted audio, video and data program signal components, wherein respective program signal components occur in signal packets including a signal payload and a service channel identifier, SCID, with different components having different SCID's, a method for detecting program components characterized by: providing a signal including said program signal components; determining from said signal, SCID's associated with respective components of respective programs; programming a plurality of programmable matched filters with SCID's determined from said signal; matched filtering said signal with said plurality of programmable matched filters, to determine the occurrence of SCID's programmed into said programmable matched filters; coupling said signal to respective audio, video and data processing elements responsive to the detection of corresponding SCID's.

Claim 13

The method set forth in claim 12 further characterized by prioritizing the programmable matched filters such that for concurrent determination of an SCID by more than one of said programmable matched, responses by all but one of the programmable matched filters is inhibited.

Claim 14

The method set forth in claim 12 characterized in that said receiver includes memory management means which is reconfigurable to accommodate respective program components, respective matched filters include programmable registers and the step of programming the programmable matched filters includes; determining if a respective matched filter which is to be reprogrammed is currently providing a control signal, and if it is providing a control signal waiting until said control signal terminates; reprogramming said programmable register with a partial new identifier and concurrently inhibiting the matched filter from providing an output; reconfiguring said memory management means; reprogramming said programmable register with a remainder of said new identifier; and enabling the output response of said matched filter.

Claim 15

In programmable apparatus for detecting predetermined signal packets of data containing desired program components from a stream of signal packets by detecting predetermined identifiers within respective packets, including programmable registers programmed with N-bit identifiers of said predetermined packets (N an integer), and respective comparing means coupled to respective programmable registers for generating control signals when an N-bit identifier contained in said programmable register matches an N-bit identifier contained in a signal packet in said stream of signal packets, and further including memory management means which is reconfigurable to accommodate respective said program components, a method of reprogramming said programmable registers characterized by: determining if a respective comparing means coupled to a programmable register which is to be reprogrammed is currently providing a control signal, and if it is providing a control signal waiting until said control signal terminates; reprogramming said programmable register with a partial new identifier and concurrently disabling said comparing means; reconfiguring said memory management means; reprogramming said programmable register with a remainder of said new identifier; and enabling said comparing means.