EP0675543A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor device including protection means and manufacturing method thereof
Assignee: Seiko Instruments Inc
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Filing: 1995-03-31
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Granted: —
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Expires: 2015-03-31
Abstract
Abstract An improvement of a resistance to electrostatic discharge of a semiconductor integrated circuit device is provided. An IC having a high ESD immunity is realised by causing a surface concentration of N type impurities in a drain area (409) of an N-channel type MOS transistor to be more than 5 E 18/cm 3 and in the direction of a source area (401) to have a monotonously decreasing concentration profile in which there is no kink in a portion less than 5 E 18/cm 3 in the surface region under a gate electrode (410).
Inventors
- 👤 Yutaka C/O Seiko Instruments Inc. Saitoh
- 👤 Jun C/O Seiko Instruments Inc. Osanai
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 14:47
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H10D89/811; H10D89/813; H10D89/815; H10D8/00
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
107 words
A semiconductor device including an N-channel MOS transistor and characterised in that a second conductive drain area (409) and a source area (401) are formed apart near the surface of a first conductive semiconductor substrate, and a gate electrode (410) is formed on a gate insulating film on said semiconductor substrate between said drain area and said source area, wherein said drain area has more than 5 x 10¹⁸ cm⁻³ of maximum impurity concentration and the impurity concentration of said drain area at the surface of said semiconductor substrate is distributed such that it monotonously decreases in the direction of said source area under said gate electrode.
Claim 2
Dependent Claim
43 words
A semiconductor device according to claim 1, wherein said drain area and said gate electrode have an overlap portion separated by said gate insulating film and the length of said overlap portion in the direction of said source area is more than 5µm.
Claim 3
Dependent Claim
29 words
A semiconductor device according to claim 1 or claim 2, wherein the semiconductor device has a structure in which said gate electrode is electrically connected with said source area.
Claim 4
Dependent Claim
30 words
A semiconductor device according to claim 1, wherein the semiconductor device has a structure in which said gate electrode is formed in a plane and continuously surrounds said drain area.
Claim 5
Dependent Claim
61 words
A semiconductor device according to any preceding claim, wherein said N-channel MOS transistor performs a bipolar operation when said gate area and said source area are electrically earthed and a voltage is applied stepwise to said drain area, and a hold voltage in said bipolar operation is greater than the upper limit voltage of operating power voltage of said semiconductor device.
Claim 6
Dependent Claim
102 words
A semiconductor device according to any preceding claim and further comprising an external terminal and an internal circuit containing a MOS transistor on said semiconductor substrate, said external terminal and said internal circuit being electrically connected, said external terminal being electrically connected with said N-channel MOS transistor, said N-channel MOS transistor performing a bipolar operation when said gate area and said source area are electrically earthed and a voltage is applied stepwise to said drain area, and a trigger voltage in said bipolar operation being lower than a trigger voltage in a bipolar operation of the MOS transistor in said internal circuit.
Claim 7
Dependent Claim
41 words
A semiconductor device according to any preceding claim and further comprising an internal circuit containing a MOS transistor on said semiconductor substrate and said N-channel MOS transistor being provided by being electrically connected between an external circuit and said internal circuit.
Claim 8
Dependent Claim
34 words
A semiconductor device according to claim 7, further comprising at least two terminals for supplying power to said internal circuit, wherein said N-channel MOS transistor is interposed and electrically connected between said two terminals.
Claim 9
Dependent Claim
22 words
A semiconductor device according to any preceding claim, wherein the semiconductor device operates with less than 1.5 volts of minimum operating voltage.
Claim 10
Dependent Claim
22 words
A semiconductor device according to any preceding claim, wherein the semiconductor device operates with more than 12 volts of maximum operating voltage.
Claim 11
Dependent Claim
22 words
A semiconductor device according to any preceding claim, wherein said semiconductor substrate is formed on a support substrate via an insulating film.
Claim 12
Dependent Claim
33 words
A semiconductor device according to claim 7 or claim 8, wherein a size of one side of a chip comprising said semiconductor substrate is less than 1.5 mm in terms of flat shape.
Claim 13
Dependent Claim
63 words
A semiconductor device according to any one of claims 1 to 5, and further comprising a switching transistor for inputting a predetermined voltage, a switch control circuit for controlling said switching transistor, a coil electrically connected with said switching transistor and a switching regulator having a structure in which said N-channel MOS transistor is electrically connected between said switching transistor and said coil.
Claim 14
Dependent Claim
49 words
A semiconductor device according to any one of claims 1 to 5 and further comprising an input terminal, an internal circuit electrically connected with said input terminal and an electrostatic protection element electrically connected with said input terminal, said electrostatic protection element being made from said N-channel MOS transistor.
Claim 15
Dependent Claim
30 words
A semiconductor device according to claim 14, wherein said drain area of said N-channel MOS transistor is electrically connected with said input terminal and said source area is electrically earthed.
Claim 16
Dependent Claim
24 words
A semiconductor device according to claim 14 or claim 15, wherein said input terminal and said internal circuit are electrically connected via a resistor.
Claim 17
Dependent Claim
49 words
A semiconductor device according to any one of claims 1 to 5 and further comprising an output terminal, an internal circuit electrically connected with said output terminal and an electrostatic protection element electrically connected with said output terminal, said electrostatic protection element being made from said N-channel MOS transistor.
Claim 18
Dependent Claim
30 words
A semiconductor device according to claim 17, wherein said drain area of said N-channel MOS transistor is electrically connected with said output terminal and said source area is electrically earthed.
Claim 19
Dependent Claim
24 words
A semiconductor device according to claim 17 or claim 18, wherein said output terminal and said internal circuit are electrically connected via a resistor.
Claim 20
Dependent Claim
59 words
A semiconductor device according to any one of claims 17 to 19, wherein an output section of said internal circuit comprises an inverter composed of a pair of transistors, one NMOS and one PMOS, an output section of said inverter is electrically connected with said output terminal and said NMOS transistor of the pair is said N-channel MOS transistor.
Claim 21
Dependent Claim
48 words
A semiconductor device according to any one of claims 17 to 20, wherein an output section of said internal circuit comprises an open drain transistor, said open drain transistor is electrically connected with said output terminal and said N-channel MOS transistor is electrically connected with said output terminal.
Claim 22
Dependent Claim
22 words
A semiconductor device according to claim 21, wherein said open drain transistor is electrically connected with said output terminal via a resistor.
Claim 23
Dependent Claim
48 words
A semiconductor device according to any one of claims 17 to 22, wherein said gate electrode of said N-channel MOS transistor is electrically connected with an output section of said internal circuit and said drain area of said N-channel MOS transistor is electrically connected with said output terminal.
Claim 24
Dependent Claim
49 words
A semiconductor device according to any one of claims 1 to 5 and further comprising an input/output terminal, an internal circuit electrically connected with said input/output terminal and an electrostatic protection element electrically connected with said input/output terminal, said electrostatic protection element being made from said N-channel MOS transistor.
Claim 25
Dependent Claim
75 words
A semiconductor device according to claim 24 and further comprising first and second inverters each composed of an NMOS transistor and PMOS transistor pair, an input section of said first inverter being connected with said input/output terminal and an output section thereof being connected with said internal circuit, respectively, and an output section of said second inverter being connected with said input/output terminal and an input section thereof being connected with said internal circuit, respectively.
Claim 26
Dependent Claim
18 words
A semiconductor device according to claim 25, wherein said NMOS transistor is made from said N-channel MOS transistor.
Claim 27
Dependent Claim
64 words
A semiconductor device according to any one of claims 1 to 5 and further comprising an internal circuit which operates with less than 5 volts of power voltage and an output terminal electrically connected with said internal circuit, said output terminal being electrically connected with said N-channel MOS transistor and with an external circuit which operates with more than 12 volts of power voltage.
Claim 28
Dependent Claim
59 words
A semiconductor device according to claim 27, wherein said internal circuit and said output terminal are electrically connected via an NMOS transistor, a gate of said NMOS transistor and said internal circuit are electrically connected, a drain of said NMOS transistor is electrically connected with said output terminal and said NMOS transistor is made from said N-channel MOS transistor.
Claim 29
Independent Claim
52 words
A method for manufacturing a semiconductor device characterised by comprising the steps of: introducing more than 5 x 10¹⁴/cm² of first counter-conductive impurities surface-selectively at least to a first conductive semiconductor substrate; forming a gate insulating film; forming a gate electrode; and introducing more than 1 x 10¹⁵/cm² of second counter-conductive impurities.
Claim 30
Independent Claim
50 words
A method for manufacturing a semiconductor device characterised by comprising the steps of: forming a gate electrode at least on a first conductive semiconductor substrate; introducing first counter-conductive impurities surface-selectively; forming a side wall spacer on the gate electrode; and introducing more than 3 x 10¹⁵/cm² of second counter-conductive impurities.
Claim 31
Independent Claim
44 words
A method for manufacturing a semiconductor device characterised by comprising the steps of: forming a gate electrode at least on a first conductive semiconductor substrate; forming a side wall spacer on the gate electrode; and introducing more than 3 x 10¹⁵/cm² of counter-conductive impurities.
References Cited (Backward Citations)
No citation records indexed.
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