EP0671767A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor antifuse structure and method
Assignee: Advanced Micro Devices Inc
•
Filing: 1990-07-10
•
Granted: —
•
Expires: 2010-07-10
Abstract
Abstract A method for forming an array of antifuse structures on a semiconductor substrate which previously has had CMOS devices fabricated thereupon up to first metallization. A fuse structure is formed as a sandwich by successively depositing a bottom layer of TiW, a layer of amorphous silicon, and a top layer of TiW. The amorphous silicon is formed in an antifuse via formed in a dielectric layer covering the bottom layer of TiW. First metallization is deposited and patterned over the top layer of TiW. An intermetal dielectric layer is formed over the fuse array and second metal conductors are formed thereupon. An alternative embodiment includes forming an oxide sidewall spacer around the periphery of an antifuse structure. Connection resistance to the bottom layer of TiW is lowered by using a number of vias between the second-metal conductors and the bottom layer of TiW in a row of an array of antifuse devices.
Inventors
- 👤 Kathryn E. Gordon
- 👤 Chin S. Jenq
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 19:56
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/491
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
230 words
A method of forming an antifuse structure comprising the steps of: providing a silicon substrate (72) which has been processed with CMOS process steps through contact formation and which has circuit elements formed thereon; forming a protective layer (116) over the circuit elements; masking and etching said protective layer away from a fuse area (118); depositing a first layer (120) of TiW over said fuse area; depositing a layer (122) of antifuse silicon material over said first layer of TiW; depositing a second layer (124) of TiW over said layer of antifuse silicon material; masking and etching said first layer of TiW, said layer of antifuse silicon material, and said second layer of TiW to form a TiW-Si-TiW antifuse sandwich; depositing an oxide layer and etching a sidewall spacer (128) from said oxide layer around the periphery of said TiW-Si-TiW antifuse sandwich; removing the protective layer; depositing a layer (138) of first conductor material over said second layer of TiW and over said circuit elements; etching portions of the layer of the first conductor material and said second layer of TiW; forming a planarized dielectric layer over said substrate; forming a via mask and etching standard vias to said layer of first conductor material and etching pick-up vias to said first layer of TiW; and depositing and etching a layer of a second conductor material over said planarized dielectric layer.
Claim 2
Independent Claim
230 words
A method of forming an antifuse structure comprising the steps of: providing a silicon substrate (72) which has been processed with CMOS process steps through contact formation and which has circuit elements formed thereon; forming a protective layer (116) over the circuit elements; masking and etching said protective layer away from a fuse area (118); depositing a first layer (120) of TiW over said fuse area; depositing a layer (122) of antifuse silicon material over said first layer of TiW; depositing a second layer (124) of TiW over said layer of antifuse silicon material; masking and etching said first layer of TiW, said layer of antifuse silicon material, and said second layer of TiW to form a TiW-Si-TiW antifuse sandwich; depositing an oxide layer and etching a sidewall spacer (128) from said oxide layer around the periphery of said TiW-Si-TiW antifuse sandwich; removing the protective layer; depositing a layer (138) of first conductor material over said second layer of TiW and over said circuit elements; etching portions of the layer of the first conductor material and said second layer of TiW; forming a planarized dielectric layer over said substrate; forming a via mask and etching standard vias to said layer of first conductor material and etching pick-up vias to said first layer of TiW; and depositing and etching a layer of a second conductor material over said planarized dielectric layer.
Claim 3
Dependent Claim
16 words
The method as claimed in claim 1 wherein said protective layer is a layer of TiW.
Claim 4
Dependent Claim
13 words
The method as claimed in claim 1 wherein said protective layer is aluminum.
Claim 5
Dependent Claim
33 words
The method as claimed in claim 1, 2 or 3 including the step of depositing a layer of a barrier metal prior to depositing the layer of first conductor material over circuit elements.
Claim 6
Independent Claim
21 words
The method as claimed in any of claims 1 to 4 wherein said antifuse silicon is a layer of amorphous silicon.
Claim 7
Dependent Claim
133 words
An antifuse structure comprising: a semiconductor substrate (72); a first layer (120) of TiW formed on said semiconductor substrate; a layer (122) of antifuse silicon formed on said first layer of TiW; a second layer (124) of TiW formed on said layer of antifuse silicon, said first and second layers of TiW and said layer of antifuse silicon forming a vertical antifuse sandwich structure; a sidewall spacer (128) formed adjacent to and surrounding the periphery of said antifuse sandwich structure; a first metal layer (138) overlying said sidewall spacer and said antifuse sandwich structures; an intermetal dielectric layer formed over said first metal layer; and a second metal connected to the first TiW layer through a via formed in said intermetal dielectric layer to provide reduced connection resistance to said first TiW layer.
Claim 8
Dependent Claim
133 words
An antifuse structure comprising: a semiconductor substrate (72); a first layer (120) of TiW formed on said semiconductor substrate; a layer (122) of antifuse silicon formed on said first layer of TiW; a second layer (124) of TiW formed on said layer of antifuse silicon, said first and second layers of TiW and said layer of antifuse silicon forming a vertical antifuse sandwich structure; a sidewall spacer (128) formed adjacent to and surrounding the periphery of said antifuse sandwich structure; a first metal layer (138) overlying said sidewall spacer and said antifuse sandwich structures; an intermetal dielectric layer formed over said first metal layer; and a second metal connected to the first TiW layer through a via formed in said intermetal dielectric layer to provide reduced connection resistance to said first TiW layer.
Claim 9
Dependent Claim
20 words
The antifuse structure as claimed in claim 6 wherein said layer of antifuse silicon includes a layer of amorphous silicon.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.