Reduced complexity MLSE receiver using modified tap weights and symbol derotation

Claim 2

An equalizer as recited in claim 1, further CHARACTERIZED IN THAT the vector is a repetitive vector.

Claim 3

An equalizer as recited in claim 1, wherein the storage array comprises a first array of registers (e.g., 114) and a second array of registers (e.g., 116), the first array of registers for storing a first set of modified tap weights and the second array of registers for storing a second set of modified tap weights, the equalizer further CHARACTERIZED BY an address generator (e.g., 118) for generating a first address of a register from which to read a modified tap weight, the first address including a most significant bit (e.g., MSB) and least significant bits (e.g., LSBs); an exclusive OR gate (e.g., 122) having a first input, a second input and an output, the first input for receiving a signal capable of changing state, the second input for receiving the most significant bit (MSB) of the first address produced by the address generator (e.g., 118), the exclusive OR gate (e.g., 122) providing an output that is the exclusive OR of its two inputs; and a concatenation circuit (e.g., 120) for receiving the least significant bits (LSBs) of the first address of the first address from the address generator (e.g., 118) and the output from the exclusive OR, the concatenation circuit (e.g., 120) for combining the output from the exclusive OR gate (e.g., 122) with the least significant bits (LSBs) of the first address from the address generator (e.g., 118) to form a second address, whereby the first address formed by the concatenation circuit (e.g., 120) addresses a register in the first array of registers (e.g., 114) when the signal providing the first input to the exclusive OR gate (e.g., 122) is in a first state and the second address formed by the concatenation circuit (e.g., 120) addresses a register in the second array of registers (e.g., 116) when the signal providing the first input to the exclusive OR gate is in a second state.

Claim 4

An equalizer as recited in claim 3, further CHARACTERIZED BY a flip-flop (e.g., 124) providing an output, the output of the flip-flop coupled as the first input of the exclusive OR gate (e.g., 122), whereby the state of the flip-flop output determines the state of the first input to the exclusive OR gate and hence which array (e.g., 114 or 116) of registers is addressed.

Claim 5

A receiver comprising an equalizer operative to receive a signal comprised of a sequence of symbols transmitted to the receiver over a transmission channel by a transmitter, the impulse response function of the channel represented as tap weights, the equalizer for determining a maximum likelihood path representative of a sequence of symbols generated by the transmitter prior to transmission on the transmission channel, the receiver CHARACTERIZED BY means for receiving (e.g., 14) a sequence of symbols transmitted over a transmission channel; means for factoring (e.g., 14) the sequence of symbols into a magnitude portion and a phase portion; means for estimating (e.g., 14) tap weights representative of the impulse response function of the transmission channel; means for generating (e.g., 14) modified tap weights by multiplying the phase portion by the tap weights by a vector; a convolver (e.g., 172) for convolving modified tap weights with bits of possible states, modified tap weights being a product of the tap weights and a vector, the convolver having at least one multiplier (e.g., 130, 132, 134, 136, or 138), the at least one multiplier receiving a modified tap weight as a multiplier and a bit of a possible state as a multiplicand, the at least one multiplier (e.g., 130, 132, 134, 136, or 138) being an accumulator and providing the product of the modified tap weight and the bit of a possible state as a convolved output; a metric calculator (e.g., 182) for receiving the convolved output and a received symbol (e.g., 176) from the sequence of received symbols, the metric calculator providing a branch metric.

Claim 6

A receiver as recited in claim 5, CHARACTERIZED BY the phase portion being repetitive.

Claim 7

A receiver as recited in claim 5, further CHARACTERIZED BY a storage array (e.g., 112) comprising a first array of registers (e.g., 114) and a second array of registers (e.g., 116), the first array of registers (e.g., 114) for storing a first set of modified tap weights and the second array of registers (e.g., 116) for storing a second set of modified tap weights; an address generator (e.g., 118) for generating a first address of a register from which to read a modified tap weight, the first address including a most significant bit (e.g., MSB) and least significant bits (e.g., LSBs); an exclusive OR gate (e.g., 122) having a first input, a second input and an output, the first input for receiving a signal capable of changing state, the second input for receiving the most significant bit (e.g., MSB) of the first address produced by the address generator (e.g., 118), the exclusive OR gate (e.g., 122) providing an output that is the exclusive OR of its two inputs; and a concatenation circuit (e.g. 120) for receiving the least significant bits (LSBs) of the first address from the address generator (e.g., 118) and the output from the exclusive OR, the concatenation circuit (e.g., 120) for combining the output from the exclusive OR gate (e.g., 122) with the least significant bits (e.g., LSBs) of the first address from the address generator (e.g., 118) to form a second address, whereby the second address formed by the concatenation circuit (e.g., 120) addresses a register in the first array of registers (e.g., 114) when the signal providing the first input to the exclusive OR gate (e.g., 122) is in a first state and the address formed by the concatenation circuit (e.g., 120) addresses a register in the second array of registers (e.g., 116) when the signal providing the first input to the exclusive OR gate is in a second state.

Claim 8

A receiver as recited in claim 7, further CHARACTERIZED BY a flip-flop (e.g., 124) providing an output, the output of the flip-flop coupled as the first input of the exclusive OR gate (e.g., 122), whereby the state of the flip-flop output determines the state of the first input to the exclusive OR gate and hence which (e.g., 114 or 116) array of registers is addressed.

Claim 10

A method of generating a detected symbol as recited in claim 9, further CHARACTERIZED BY the steps of: multiplying (e.g., 202) a rotating vector (e.g., 200) times a received symbol (e.g., 176) from the sequence of received symbols to provide a derotated received symbol (e.g., 204); and utilizing the derotated received symbol (e.g., 204) in performing a MLSE (e.g., 182, 184) on a received symbol, whereby derotation is achieved before equalization.

Claim 11

A method of generating a detected symbol as recited in claim 9, further CHARACTERIZED BY the step of: multiplying (e.g., 192) the MLSE detected symbol (e.g., 188) by a rotating vector (e.g., 190), whereby derotation is achieved after equalization.

Claim 12

A receiver operative to receive a signal comprised of a sequence of symbols transmitted by a transmitter to the receiver over a transmission channel, the detected symbol being the most likely symbol to have been transmitted of all possible symbols that could have been transmitted, the receiver CHARACTERIZED BY: means for receiving a sequence of symbols (e.g., 14) transmitted over a transmission channel; means for estimating tap weights (e.g., 14) representative of the impulse response function of the channel; means for factoring (e.g., 14) the received sequence of symbols into a magnitude portion and a repetitive phase portion; means for multiplying (e.g., 14) the tap weights representative of the channel by the repetitive phase portion to generate modified tap weights; means for convolving (e.g., 172) the modified tap weights with bits of a possible state to generate a transmitted symbol estimate (e.g., 174); and means for performing a maximum likelihood sequence estimation (MLSE) (e.g., 182, 184) on a received symbol to identify a maximum likelihood transmitted symbol as the detected symbol.

Claim 13

A receiver as recited in claim 12, further CHARACTERIZED BY means for multiplying (e.g., 202) a rotating vector (e.g., 200) by a received symbol (e.g., 176) from the sequence of received symbols to provide a derotated received symbol (e.g., 204); and means for utilizing the derotated received symbol (e.g., 204) in performing a MLSE (e.g., 182, 184) on a received symbol, whereby derotation is achieved before equalization.

Claim 14

A receiver as recited in claim 12, further CHARACTERIZED BY means for multiplying (e.g., 192) the MLSE detected symbol (e.g., 188) by a rotating vector (e.g., 190) whereby derotation is achieved after equalization.

Claim 15

A method as claimed in claim 9 or a receiver as claimed in claim 12, wherein the bits of a possible state convolved with the modified tap weights include the bits of all possible states.