EP0669655A2
Expired / Lapsed
EP
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Ferroelectric capacitor renewal method
Assignee: Ramtron International Corp
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Filing: 1994-11-30
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Granted: —
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Expires: 2014-11-30
Abstract
Abstract Ferroelectric capacitors in an integrated memory are renewed to improve retention performance. The renewal method is performed on a wafer containing ferroelectric memory die. In one method, a rejuvenation anneal is performed after all electrical tests, including those at elevated temperatures, have been accomplished, but before the failed die have been inked. The rejuvenation anneal is performed at or above the Curie temperature of the ferroelectric material. In the preferred embodiment, the ferroelectric material is PZT, and the rejuvenation anneal is a thermal treatment at 400 ° Centigrade in a nitrogen flow of roughly ten liters per minute for about an hour. In another method, separate electrical cycling and depoling operations are performed to provide the equivalent benefits of the single rejuvenation anneal. The electrical cycling operation is accomplished by writing about one hundred cycles at five volts alternating logic states into each ferroelectric capacitor into the array. The electrical cycling operation restores the symmetry and location of the hysteresis loop. The ferroelectric capacitor is then returned to the virgin state by a depoling operation. The electrical depoling operation is achieved by writing each capacitor in the array to a logic one and a logic zero at the full five volt power supply level initially, and then repeating each write cycle at decreasing power supply levels. The writing cycles are continued until the power supply is reduced to a minimum functional level and the polarization on the capacitors has been substantially removed.
Inventors
- 👤 Stan Perino
- 👤 Sanjay Mitra
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 04:26
CPC Classifications
H; H10; H10B; H10B53/00; H10B53/30
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
102 words
A method of manufacturing ferroelectric memories comprising the steps of: fabricating a plurality of ferroelectric memory integrated circuits on a wafer; thermally treating the wafer at a first temperature less than the Curie temperature of the ferroelectric material in the memory circuits; electrically testing the memory circuits to identify bad die that have failed the electrical test and good die that have passed the electrical test; and annealing the wafer at a second temperature equal to or greater than the Curie temperature of the ferroelectric material in the memory circuits to restore a substantially virgin state of polarization in the ferroelectric capacitors.
Claim 2
Independent Claim
102 words
A method of manufacturing ferroelectric memories comprising the steps of: fabricating a plurality of ferroelectric memory integrated circuits on a wafer; thermally treating the wafer at a first temperature less than the Curie temperature of the ferroelectric material in the memory circuits; electrically testing the memory circuits to identify bad die that have failed the electrical test and good die that have passed the electrical test; and annealing the wafer at a second temperature equal to or greater than the Curie temperature of the ferroelectric material in the memory circuits to restore a substantially virgin state of polarization in the ferroelectric capacitors.
Claim 3
Dependent Claim
26 words
The method of claim 1 in which the annealing step further comprises the step of exposing the wafer to a nitrogen flow for about an hour.
Claim 4
Dependent Claim
24 words
The method of claim 1 in which the annealing step is conducted in a nitrogen flow of about ten liters of nitrogen per minute.
Claim 5
Dependent Claim
28 words
The method of claim 1 in which the fabricating step comprising the step of fabricating a plurality of non-volatile PZT ferroelectric memory integrated circuits on a silicon wafer.
Claim 6
Dependent Claim
20 words
The method of claim 4 in which the annealing step is conducted at a temperature of about 400 ° C.
Claim 7
Dependent Claim
43 words
The method of claim 1 in which the electrical testing step comprises the steps of: reading a first data state stored in the ferroelectric capacitors in the memory integrated circuit; and subsequently reading a second data state opposite to the first data state.
Claim 8
Dependent Claim
14 words
The method of claim 1 further comprising the steps of inking the bad die.
Claim 9
Dependent Claim
21 words
The method of claim 7 further comprising the steps of: creating individual die from the wafer; and packaging the good die.
Claim 10
Dependent Claim
25 words
The method of claim 8 in which the step of packaging the good die comprises the step of packaging the good die in plastic packages.
Claim 11
Dependent Claim
36 words
The method of claim 1 in which the fabricating step includes the step of creating a ferroelectric capacitor stack and associated electrical interconnection of sufficient mechanical and thermal integrity to withstand the annealing step without damage.
Claim 12
Dependent Claim
50 words
A manufacturing method for an integrated circuit PZT ferroelectric memory that is performed on a wafer including a plurality of the ferroelectric memories, the method comprising the step of annealing the wafer at about 400 C in a nitrogen flow of about ten liters per minute for about an hour.
Claim 13
Dependent Claim
50 words
A manufacturing method for an integrated circuit PZT ferroelectric memory that is performed on a wafer including a plurality of the ferroelectric memories, the method comprising the step of annealing the wafer at about 400 C in a nitrogen flow of about ten liters per minute for about an hour.
Claim 14
Dependent Claim
98 words
A renewal method for imprinted ferroelectric capacitors in an integrated circuit memory comprising the steps of: fabricating a plurality of ferroelectric memory integrated circuits on a silicon wafer; thermally treating the wafer at a first temperature less than the Curie temperature of the ferroelectric material in the memory circuits; electrically testing the memory circuits at the wafer level to identify bad die that have failed the electrical test and good die that have passed the electrical test; electrically cycling the memory circuits; and electrically depoling the memory circuits to restore a substantially virgin state in the ferroelectric capacitors.
Claim 15
Dependent Claim
98 words
A renewal method for imprinted ferroelectric capacitors in an integrated circuit memory comprising the steps of: fabricating a plurality of ferroelectric memory integrated circuits on a silicon wafer; thermally treating the wafer at a first temperature less than the Curie temperature of the ferroelectric material in the memory circuits; electrically testing the memory circuits at the wafer level to identify bad die that have failed the electrical test and good die that have passed the electrical test; electrically cycling the memory circuits; and electrically depoling the memory circuits to restore a substantially virgin state in the ferroelectric capacitors.
Claim 16
Dependent Claim
30 words
The method of claim 12 in which the electrical cycling step comprises the step of repetitively alternating opposite data states into each of the ferroelectric capacitors in the memory circuits.
Claim 17
Dependent Claim
41 words
The method of claim 12 in which the electrical cycling step is accomplished by writing about one hundred cycles of alternating opposite data states into each of the ferroelectric capacitors in the memory circuits at a full power supply voltage level.
Claim 18
Dependent Claim
34 words
The method of claim 12 in which the electrical depoling step comprises the step of writing opposite data states into each of the ferroelectric capacitors in the memory circuits at sequentially decreasing voltage levels.
Claim 19
Dependent Claim
85 words
The method of claim 12 in which the electrical depoling step comprises the steps of: (a) writing opposite data states into each of the ferroelectric capacitors in the memory circuit at the full power supply voltage level; (b) reducing the writing voltage by a predetermined incremental voltage; (c) writing opposite data states into each of the ferroelectric capacitors in the memory circuit at the reduced voltage; (d) repeating steps (b) and (c) until the writing voltage has been reduced to a predetermined minimum voltage level.
Claim 20
Dependent Claim
43 words
The method of claim 12 in which the electrical testing step comprises the steps of: reading a first data state stored in the ferroelectric capacitors in the memory integrated circuit; and subsequently reading a second data state opposite to the first data state.
Claim 21
Dependent Claim
14 words
The method of claim 12 further comprising the steps of inking the bad die.
Claim 22
Dependent Claim
21 words
The method of claim 18 further comprising the steps of: creating individual die from the wafer; and packaging the good die.
Claim 23
Dependent Claim
25 words
The method of claim 19 in which the step of packaging the good die comprises the step of packaging the good die in plastic packages.
Claim 24
Dependent Claim
47 words
A renewal method for an integrated circuit ferroelectric memory performed on a wafer including a plurality of memory circuits, wherein each memory circuit includes a plurality of ferroelectric capacitors, the method comprising the steps of: electrically cycling the memory circuits; and subsequently electrically depoling the memory circuits.
Claim 25
Dependent Claim
47 words
A renewal method for an integrated circuit ferroelectric memory performed on a wafer including a plurality of memory circuits, wherein each memory circuit includes a plurality of ferroelectric capacitors, the method comprising the steps of: electrically cycling the memory circuits; and subsequently electrically depoling the memory circuits.
Claim 26
Dependent Claim
83 words
The method of claim 21 in which the electrical depoling step comprises the steps of: (a) writing opposite data states into each of the ferroelectric capacitors in the memory circuit at a full power supply voltage level; (b) subsequently reducing the writing voltage; (c) subsequently writing opposite data states into each of the ferroelectric capacitors in the memory circuit at the reduced voltage; and (d) repeating steps (b) and (c) until the writing voltage has been reduced to a predetermined minimum voltage level.
Claim 27
Dependent Claim
27 words
The method of claim 22 in which the step of reducing the writing voltage comprises the step of reducing the writing voltage by a predetermined incremental voltage.
Claim 28
Dependent Claim
95 words
A renewal method for avoiding imprinting of ferroelectric capacitors in an integrated circuit memory comprising the steps of: fabricating a plurality of ferroelectric memory integrated circuits on a silicon wafer; thermally treating the wafer at a first temperature less than the Curie temperature of the ferroelectric material in the memory circuits; electrically testing the memory circuits at the wafer level to identify bad die that have failed the electrical test and good die that have passed the electrical test; and electrically depoling the memory circuits to restore a substantially virgin state in the ferroelectric capacitors.
Claim 29
Dependent Claim
95 words
A renewal method for avoiding imprinting of ferroelectric capacitors in an integrated circuit memory comprising the steps of: fabricating a plurality of ferroelectric memory integrated circuits on a silicon wafer; thermally treating the wafer at a first temperature less than the Curie temperature of the ferroelectric material in the memory circuits; electrically testing the memory circuits at the wafer level to identify bad die that have failed the electrical test and good die that have passed the electrical test; and electrically depoling the memory circuits to restore a substantially virgin state in the ferroelectric capacitors.
Claim 30
Dependent Claim
34 words
The method of claim 24 in which the electrical depoling step comprises the step of writing opposite data states into each of the ferroelectric capacitors in the memory circuits at sequentially decreasing voltage levels.
Claim 31
Dependent Claim
85 words
The method of claim 24 in which the electrical depoling step comprises the steps of: (a) writing opposite data states into each of the ferroelectric capacitors in the memory circuit at the full power supply voltage level; (b) reducing the writing voltage by a predetermined incremental voltage; (c) writing opposite data states into each of the ferroelectric capacitors in the memory circuit at the reduced voltage; (d) repeating steps (b) and (c) until the writing voltage has been reduced to a predetermined minimum voltage level.
Claim 32
Dependent Claim
14 words
The method of claim 24 further comprising the steps of inking the bad die.
Claim 33
Dependent Claim
21 words
The method of claim 27 further comprising the steps of: creating individual die from the wafer; and packaging the good die.
Claim 34
Dependent Claim
25 words
The method of claim 28 in which the step of packaging the good die comprises the step of packaging the good die in plastic packages.
Claim 35
Independent Claim
74 words
A method of fabricating ferroelectric memories in which a plurality of memory circuits are formed on a wafer, the circuits are electrically tested and those which pass the test are subsequently packaged, characterised by the step of performing a de-imprinting operation prior to the packaging step so as to restore the ferroelectric material of at least the circuits which pass the electrical test to a state in which their hysteresis loops are substantially symmetrical.
Claim 36
Independent Claim
74 words
A method of fabricating ferroelectric memories in which a plurality of memory circuits are formed on a wafer, the circuits are electrically tested and those which pass the test are subsequently packaged, characterised by the step of performing a de-imprinting operation prior to the packaging step so as to restore the ferroelectric material of at least the circuits which pass the electrical test to a state in which their hysteresis loops are substantially symmetrical.
References Cited (Backward Citations)
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