EP0668562A1 — Method for programming redundancy registers in a …

Claim 1

Independent Claim 241 words

Method for programming redundancy registers in a column redundancy integrated circuitry for a semiconductor memory device with memory elements located at the intersection of rows and columns of at least one bidimensional array of memory elements, the columns being grouped together to form portions of the bidimensional array, the column redundancy circuitry comprising at least one respective plurality of non-volatile memory registers (RR1-RR4) each one associated to a respective redundancy column of redundancy memory elements and each one programmable to store an address of a defective column and an identifying code (MCS7-MCS10) for identifying the portion of the bidimensional array to which the defective column belongs, characterized in that it provides for supplying each non-volatile memory register (RR1-RR4) with column address signals (CABUS) and with a first set of signals (R1-R4), constituting a first subset of a set of row address signals (RABUS), which when one of the non-volatile memory registers (RR1-RR4) is to be programmed carry the address of a defective column and said identifying code (MCS7-MCS10) respectively, and for activating one signal of a second set of signals (R5-R8), supplied to programming selection means (6) and constituting a second subset of the set of row address signals (RABUS), for selecting one respective non-volatile memory register (RR1-RR4) of said plurality to cause the data carried by the column address signals (CABUS) and by the first set of signals (R1-R4) to be programmed into said one respective non-volatile memory register (RR1-RR4).

Claim 2

Dependent Claim 241 words

Method for programming redundancy registers in a column redundancy integrated circuitry for a semiconductor memory device with memory elements located at the intersection of rows and columns of at least one bidimensional array of memory elements, the columns being grouped together to form portions of the bidimensional array, the column redundancy circuitry comprising at least one respective plurality of non-volatile memory registers (RR1-RR4) each one associated to a respective redundancy column of redundancy memory elements and each one programmable to store an address of a defective column and an identifying code (MCS7-MCS10) for identifying the portion of the bidimensional array to which the defective column belongs, characterized in that it provides for supplying each non-volatile memory register (RR1-RR4) with column address signals (CABUS) and with a first set of signals (R1-R4), constituting a first subset of a set of row address signals (RABUS), which when one of the non-volatile memory registers (RR1-RR4) is to be programmed carry the address of a defective column and said identifying code (MCS7-MCS10) respectively, and for activating one signal of a second set of signals (R5-R8), supplied to programming selection means (6) and constituting a second subset of the set of row address signals (RABUS), for selecting one respective non-volatile memory register (RR1-RR4) of said plurality to cause the data carried by the column address signals (CABUS) and by the first set of signals (R1-R4) to be programmed into said one respective non-volatile memory register (RR1-RR4).

Claim 3

Dependent Claim 250 words

Column redundancy integrated circuitry for a semiconductor memory device with memory elements located at the intersection of rows and columns of at least one bidimensional array of memory elements, the columns being grouped together to form portions of the bidimensional array, comprising at least one respective plurality of non-volatile memory registers (RR1-RR4) each one associated to a respective redundancy column of redundancy memory elements and each one programmable to store an address of a defective column and an identifying code (MCS7-MCS10) for identifying the portion of the bidimensional array to which the defective column belongs, characterized in that it comprises first means (CABUS) and second means (RABUS') for supplying each non-volatile memory register (RR1-RR4) respectively with column address signals (C1-C6) and with a first set of signals (R1-R4), constituting a first subset of a set of row address signals (RABUS), which when one of the non-volatile memory registers (RR1-RR4) is to be programmed carry the address of a defective column and said identifying code (MCS7-MCS10) respectively, and in that it further comprises programming selection means (6) supplied with a second set of signals (R5-R8), constituting a second subset of the set of row address signals (RABUS), each signal of said second set (R5-R8) being associated to a respective non-volatile memory register (RR1-RR4) of said at least one plurality to cause, when activated, the data carried by the column address signals (C1-C6) and by the first set of signals (R1-R4) to be programmed into the respective associated non-volatile memory register (RR1-RR4).

Claim 4

Dependent Claim 250 words

Column redundancy integrated circuitry for a semiconductor memory device with memory elements located at the intersection of rows and columns of at least one bidimensional array of memory elements, the columns being grouped together to form portions of the bidimensional array, comprising at least one respective plurality of non-volatile memory registers (RR1-RR4) each one associated to a respective redundancy column of redundancy memory elements and each one programmable to store an address of a defective column and an identifying code (MCS7-MCS10) for identifying the portion of the bidimensional array to which the defective column belongs, characterized in that it comprises first means (CABUS) and second means (RABUS') for supplying each non-volatile memory register (RR1-RR4) respectively with column address signals (C1-C6) and with a first set of signals (R1-R4), constituting a first subset of a set of row address signals (RABUS), which when one of the non-volatile memory registers (RR1-RR4) is to be programmed carry the address of a defective column and said identifying code (MCS7-MCS10) respectively, and in that it further comprises programming selection means (6) supplied with a second set of signals (R5-R8), constituting a second subset of the set of row address signals (RABUS), each signal of said second set (R5-R8) being associated to a respective non-volatile memory register (RR1-RR4) of said at least one plurality to cause, when activated, the data carried by the column address signals (C1-C6) and by the first set of signals (R1-R4) to be programmed into the respective associated non-volatile memory register (RR1-RR4).

Claim 5

Dependent Claim 127 words

Column redundancy integrated circuitry according to claim 2, characterized in that each non-volatile memory register (RR1-RR4) comprises a first set of non-volatile memory cells (MC1-MC6) each supplied with a respective column address signal (C1-C6), and a second set of non-volatile memory cells (MC7-MC10) each supplied with a respective signal of the first set of signals (R1-R4), each memory cell (MC1-MC10) comprising at least one programmable non-volatile memory element (M1), a load circuit (LC) for reading the information stored in said non-volatile memory element (M1), and a programming load circuit (M2) for electrically connecting said non-volatile memory element (M1) to the respective column address signal (C1-C6) or to the respective signal of the first set of signals (R1-R4) when the non-volatile memory register (RR1-RR4) is to be programmed.

Claim 6

Dependent Claim 81 words

Column redundancy integrated circuitry according to claim 3, characterized in that said programming load circuit comprises a transistor (M2) connected between one of said column address signals (C1-C6) or one signal of the first set of signals (R1-R4) and a supply electrode of the respective non-volatile memory element (M1), and controlled by a program enable signal (PGEN1-PGEN4) which during programming is activated by said programming selection means (6) when the respective signal of the second set of signals (R5-R8) is activated.

Claim 7

Dependent Claim 88 words

Column redundancy integrated circuitry according to claim 2, the memory device comprising a plurality of bidimensional arrays of memory elements costituting individually addressable sectors of a matrix of memory elements, each sector being provided with a respective plurality of redundancy columns associated to a respective plurality of non-volatile memory registers (RR1-RR4), characterized in that said programming selection means (6) are further supplied with sector selection signals (S1-S4) for the selection of the plurality of non-volatile memory registers (RR1-RR4) to which a non-volatile memory register to be programmed belongs.

Method for programming redundancy registers in a column redundancy integrated circuitry for a semiconductor memory device

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