EP0667686A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
DS/CDMA diveristy receiver with despreading filters
Assignee: NEC Corp
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Filing: 1994-12-16
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Granted: —
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Expires: 2014-12-16
Abstract
Abstract A DS/CDMA receiver includes first and second diversity branches each including an antenna, a receiver and a despreading filter. The output signals of the transversal despreading filters of both diversity branches are diversity-combined, and threshold decision is made on the combined signal to produce a decision output. A decision error is detected from the combined signal and the decision output. Interchannel interference is canceled in each despreading filter by controlling their tap weights so that the tap weight coefficient vectors of each filter are orthogonal to all the spread codes of signals from other sources and multipath fading related intersymbol interference is canceled when the decision error of the diversity-combined signal is reduced to a minimum.
Inventors
- 👤 Toshifumi C/O Nec Corporation Sato
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 17:42
CPC Classifications
H; H04; H04B; H04B1/00; H04B1/69; H04B1/707; H04B1/7097; H04B7/00; H04B7/02; H04B7/04; H04B7/08; H04B7/0837; H04B7/0842; H04B7/0845; H04B7/0891; H04B7/0848; H04B7/0851
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
252 words
A direct-sequence code division multiple access receiver comprising: a first diversity branch having a first antenna, a first receiver connected thereto and a first despreading filter comprising a tapped delay line for successively delaying an output signal of the first receiver, a plurality of multipliers for weighting tap signals on successive taps of the tapped delay line with a first vector of tap weight coefficients and an adder for summing the weighted tap signals to produce an output signal of the first despreading filter; a second diversity branch having a second antenna, a second receiver connected thereto and a second despreading filter comprising a tapped delay line for successively delaying an output signal of the second receiver, a plurality of multipliers for weighting tap signals on successive taps of the tapped delay line with a second vector of tap weight coefficients and an adder for summing the weighted tap signals to produce an output signal of the second despreading filter; a diversity combiner for combining the output signals of said first and second despreading filters to produce a combined signal; a decision circuit for making a threshold decision on said combined signal to produce a decision output signal; means for detecting a decision error from said combined signal and said decision output signal; and control means for controlling said first and second vectors of tap weight coefficients with the tap signals of said first and second despreading filters and said decision error so that the decision error is reduced to a minimum.
Claim 2
Dependent Claim
252 words
A direct-sequence code division multiple access receiver comprising: a first diversity branch having a first antenna, a first receiver connected thereto and a first despreading filter comprising a tapped delay line for successively delaying an output signal of the first receiver, a plurality of multipliers for weighting tap signals on successive taps of the tapped delay line with a first vector of tap weight coefficients and an adder for summing the weighted tap signals to produce an output signal of the first despreading filter; a second diversity branch having a second antenna, a second receiver connected thereto and a second despreading filter comprising a tapped delay line for successively delaying an output signal of the second receiver, a plurality of multipliers for weighting tap signals on successive taps of the tapped delay line with a second vector of tap weight coefficients and an adder for summing the weighted tap signals to produce an output signal of the second despreading filter; a diversity combiner for combining the output signals of said first and second despreading filters to produce a combined signal; a decision circuit for making a threshold decision on said combined signal to produce a decision output signal; means for detecting a decision error from said combined signal and said decision output signal; and control means for controlling said first and second vectors of tap weight coefficients with the tap signals of said first and second despreading filters and said decision error so that the decision error is reduced to a minimum.
Claim 3
Dependent Claim
40 words
A direct-sequence code division multiple access receiver as claimed in claim 1, wherein said first and second vectors are controlled so that said vectors are orthogonal to spread codes of signals other than a spread code of a desired signal.
Claim 4
Dependent Claim
30 words
A direct-sequence code division multiple access receiver as claimed in claim 1, wherein said control means includes means for controlling said first and second vectors in accordance with least-mean-squares algorithm.
Claim 5
Dependent Claim
30 words
A direct-sequence code division multiple access receiver as claimed in claim 1, wherein said control means includes means for controlling said first and second vectors in accordance with recursive-least-squares algorithm.
Claim 6
Dependent Claim
202 words
A direct-sequence code division multiple access receiver as claimed in claim 1, wherein said first despreading filter further comprises means for sampling the output signal of the first receiver at twice the chip rate at which a transmitted symbol is chipped with a spreading code and producing a sampled signal and means for sampling said sum signal at intervals of said symbol to produce the output signal of said first despreading filter, wherein the tapped delay line of the first despreading filter includes a series of delay elements for successively delaying said sampled signal for a duration equal to 1/2 of the reciprocal of said chip rate, and wherein said second despreading filter further comprises means for sampling the output signal of the second receiver at twice said chip rate to produce a sampled signal and means for sampling the sum signal of the second despreading filter at intervals of said symbol to produce the output signal of said second despreading filter, wherein the tapped delay line of the second despreading filter includes a series of delay elements for successively delaying the sampled signal of the second despreading filter for a duration equal to 1/2 of the reciprocal of said chip rate.
References Cited (Backward Citations)
JPH04185130A
Cited
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