Semiconductor memory device capable of storing plural-bit data in a single memory cell

Claim 2

The device according to claim 1, characterized in that said impurity-introducing area extends from said drain region to said source region and has a predetermined width in the width direction of the channel region.

Claim 3

The device according to claim 1, characterized in that said impurity-introducing area has a predetermined length in the length direction of the channel region over the entire width of the channel region.

Claim 4

The device according to claim 2, characterized in that said impurity-introducing area has one of first to fourth states, the first state being that said impurity-introducing area extends over the entire channel region (CH), the second state being that said impurity-introducing area has a first predetermined width, the third state being that said impurity-introducing area has a second predetermined width less than said first predetermined width, the fourth state being that said impurities are not introduced into said impurity-introducing area in the stage of data programming for said memory cell of the manufacturing process, each of said first to fourth states corresponding to two bits of binary data.

Claim 5

The device according to claim 3, characterized in that said impurity-introducing area has one of first to fourth states, the first state being that said impurity-introducing area extends over the entire channel region (CH), the second state being that said impurity-introducing area has such a predetermined width as to be in contact said drain region and out of contact with said source region, the third state being that said impurity-introducing area has such a predetermined width as to be in contact with said source region and out of contact with said drain region, the fourth state being that said impurities are not introduced into said impurity-introducing area in the stage of data programming for said memory cell of the manufacturing process, each of said first to fourth states corresponding to two bits of binary data.

Claim 6

A semiconductor memory device with a plurality of memory cells, for storing data in each of the memory cells, characterized in that each of said memory cells (MC) includes a drain region (D), a source region (S), a channel region (CH), a gate electrode (G) and a gate insulating film (54) between said gate electrode and said channel region, said gate insulating film has first and second portions (54a, 54b), said first portion (54a) is formed on a portion of said channel region, said first portion has a predetermined width between said drain region and said source region and has a first thickness, and said second portion (54b) is formed on a portion of said channel region, said second portion has a predetermined width between said drain region and said source region, and said second portion has a second thickness greater than said first thickness, impurities are introduced into said channel region in a stage of data programming for said memory cell of a manufacturing process by ion implantation, and each of said memory cells has one of first to fourth states, the first state being that said impurities are introduced into said channel region below said first and second portions (54a, 54b) of said gate insulating film, the second state being that the impurities are introduced into said channel region below said first portion (54a) of said gate insulating film, the third state being that the impurities are introduced into said channel region below said second portion (54b) of said gate insulating film, the fourth state being that the impurities are not introduced into the channel region below said first and second portions (54a, 54b) of said gate insulating film in the stage of data programming for said memory cell of the manufacturing process, each of said first to fourth states corresponding to two bits of binary data.

Claim 7

A semiconductor memory device characterized by comprising: row lines (WL1 to WLn); a plurality of memory cells (MC) each having a current path, one end of the current path being connected to a first power supply (VC), said memory cell being driven by the associated one of said row lines, each memory cell having one of four threshold voltages and storing data of two bits; a column line (BL1 to BLn, L1) connected to the other end of the current path of each of the memory cells; first dummy cells (RC1) equivalent in structure to said memory cells, each having a current path, one end of the current path being connected to the first power supply (VC), said first dummy cells being driven by the associated one of said row lines, each of said first dummy cells having a first threshold voltage which is the highest of said four threshold voltages; a first dummy column line (RBL1) connected to the other end of the current path of each of the first dummy cells; second dummy cells (RC2) equivalent in structure to said memory cells, each having a current path, one end of the current path being connected to the first power supply (VC), said second dummy cells being driven by the associated one of said row lines, each of said second dummy cells having a second threshold voltage which is the second highest of said four threshold voltages; a second dummy column line (RBL2) connected to the other end of the current path of each of the second dummy cells; third dummy cells (RC3) equivalent in structure to said memory cells, each having a current path, one end of the current path being connected to the first power supply (VC), said third dummy cells being driven by the associated one of said row lines, each of said third dummy cells having a third threshold voltage which is the third highest of said four threshold voltages; a third dummy column line (RBL3) connected to the other end of the current path of each of the third dummy cells; fourth dummy cells (RC4) equivalent in structure to said memory cells, each having a current path, one end of the current path being connected to the first power supply (VC), said fourth dummy cells being driven by the associated one of said row lines, each of said fourth dummy cells having a fourth threshold voltage which is the lowest of said four threshold voltages; a fourth dummy column line (RBL4) connected to the other end of the current path of each of the fourth dummy cells; a first data sense circuit (SA1) having one end connected to said column line (L1) and the other end connected to said first and second dummy column lines (RBL1, RBL2), said first data sense circuit comparing the potential of said column line and the potentials of said first and second dummy column lines and outputting a signal; a second data sense circuit (SA2) having one end connected to said column line (L1) and the other end connected to said second and third dummy column lines (RBL2, RBL3), said second data sense circuit comparing the potential of said column line and the potentials of said second and third dummy column lines and outputting a signal; a third data sense circuit (SA3) having one end connected to said column line (L1) and the other end connected to said third and fourth dummy column lines (RBL3, RBL4), said third data sense circuit comparing the potential of said column line and the potentials of said third and fourth dummy column lines and outputting a signal; and a logic circuit (86) connected to output terminals of said first, second and third data sense circuits, said logic circuit receiving the output signals from the first, second and third data sense circuits and outputting data of two bits stored in the memory cells.

Claim 8

The device according to claim 7, characterized in that said first data sense circuit (SA1) comprises: first and second transistors (P1, P2) of a first conductivity type having gates connected to said column line (L1), sources connected to the first power supply (VC) and drains connected to each other; a third transistor (P3) of the first conductivity type having a gate connected to said first dummy column line (RBL1) and a source connected to said first power supply (VC); a fourth transistor (P4) of the first conductivity type having a gate connected to said second dummy column line (RBL2), a source connected to said first power supply (VC), and a drain connected to the drain of said third transistor; a first transistor (N1) of a second conductivity type having a drain connected to the drains of said first and second transistors, a source connected to a second power supply (Vs), and a gate connected to the drains of said third and fourth transistors; and a second transistor (N2) of the second conductivity type having a drain and a gate connected to the drains of said third and fourth transistors, and a source connected to the second power supply, said second data sense circuit (SA2) comprises: fifth and sixth transistors (P5, P6) of a first conductivity type having gates connected to said column line (L1), sources connected to a first power supply (VC) and drains connected to each other; a seventh transistor (P7) of the first conductivity type having a gate connected to said second dummy column line (RBL2) and a source connected to said first power supply (VC); an eighth transistor (P8) of the first conductivity type having a gate connected to said third dummy column line (RBL3), a source connected to said first power supply (VC), and a drain connected to the drain of said seventh transistor; a third transistor (N3) of a second conductivity type having a drain connected to the drains of said fifth and sixth transistors, a source connected to a second power supply (Vs), and a gate connected to the drains of said seventh and eighth transistors; and a fourth transistor (N4) of the second conductivity type having a drain and a gate connected to the drains of said seventh and eighth transistors, and a source connected to the second power supply, and said third data sense circuit (SA3) comprises: ninth and tenth transistors (P9, P10) of a first conductivity type having gates connected to said column line (L1), sources connected to a first power supply (VC) and drains connected to each other; an eleventh transistor (P11) of the first conductivity type having a gate connected to said third dummy column line (RBL3) and a source connected to said first power supply (VC); a twelfth transistor (P12) of the first conductivity type having a gate connected to said fourth dummy column line (RBL4), a source connected to said first power supply (VC), and a drain connected to the drain of said eleventh transistor; a fifth transistor (N5) of a second conductivity type having a drain connected to the drains of said ninth and eleventh transistors, a source connected to a second power supply (Vs), and a gate connected to the drains of said eleventh and twelfth transistors; and a sixth transistor (N6) of the second conductivity type having a drain and a gate connected to the drains of said eleventh and twelfth transistors, and a source connected to the second power supply.

Claim 9

A semiconductor memory device characterized by comprising: row lines (WL1 to WLn); a plurality of memory cells (MC) each having a current path, one end of the current path being connected to a first power supply (VC), said memory cell being driven by the associated one of said row lines, each memory cell having one of four threshold voltages and storing data of two bits; a column line (BL1 to BLn, L1) connected to the other end of the current path of each of the memory cells (MC); first dummy cells (RC1) equivalent in structure to said memory cells, each having a current path, one end of the current path being connected to the first power supply (VC), said first dummy cells being driven by the associated one of said row lines, each of said first dummy cells having a first threshold voltage which is the highest of said four threshold voltages; a first dummy column line (RBL1) connected to the other end of the current path of each of the first dummy cells; second dummy cells (RC21) equivalent in structure to said memory cells, each having a current path, one end of the current path being connected to the first power supply (VC), said second dummy cells being driven by the associated one of said row lines, each of said second dummy cells having a second threshold voltage which is the second highest of said four threshold voltages; a second dummy column line (RBL21) connected to the other end of the current path of each of the second dummy cells and connected to said first dummy column line; third dummy cells (RC22) equivalent in structure to said memory cells, each having a current path, one end of the current path being connected to the first power supply (VC), said third dummy cells being driven by the associated one of said row lines, each of said third dummy cells having the second threshold voltage which is the second highest of said four threshold voltages; a third dummy column line (RBL22) connected to the other end of the current path of each of the third dummy cells; fourth dummy cells (RC31) equivalent in structure to said memory cells, each having a current path, one end of the current path being connected to the first power supply (VC), said fourth dummy cells being driven by the associated one of said row lines, each of said fourth dummy cells having a third threshold voltage which is the third highest of said four threshold voltages; a fourth dummy column line (RBL31) connected to the other end of the current path of each of the fourth dummy cells and connected to said third dummy column line; fifth dummy cells (RC32) equivalent in structure to said memory cells, each having a current path, one end of the current path being connected to the first power supply (VC), said fifth dummy cells being driven by the associated one of said row lines, each of said fifth dummy cells having the third threshold voltage which is the third highest of said four threshold voltages; a fifth dummy column line (RBL32) connected to the other end of the current path of each of the fifth dummy cells; sixth dummy cells (RC4) equivalent in structure to said memory cells, each having a current path, one end of the current path being connected to the first power supply (VC), said sixth dummy cells being driven by the associated one of said row lines, each of said sixth dummy cells having a fourth threshold voltage which is the lowest of said four threshold voltages; a sixth dummy column line (RBL4) connected to the other end of the current path of each of the sixth dummy cells and connected to the fifth dummy column line (RBL32); a first data sense circuit (SA1) having one end connected to said column line (L1) and the other end connected to said connected first and second dummy column lines (RBL1, RBL21), said first data sense circuit comparing the potential of said one end and the potential of said other end and outputting a signal; a second data sense circuit (SA2) having one end connected to said column line (L1) and the other end connected to said connected third and fourth dummy column lines (RBL22, RBL31), said second data sense circuit comparing the potential of said one end and the potential of said other end and outputting a signal; a third data sense circuit (SA3) having one end connected to said column line (L1) and the other end connected to said connected fifth and sixth dummy column lines (RBL32, RBL4), said third data sense circuit comparing the potential of said one end and the potential of said other end and outputting a signal; and a logic circuit (86) connected to output terminals of said first, second and third data sense circuits, said logic circuit receiving the output signals from the first, second and third data sense circuits and outputting data of two bits stored in the memory cells.

Claim 10

The device according to claim 9, characterized in that said first data sense circuit (SA1) comprises: a first transistor (P21) of a first conductivity type having a gate connected to said column line (L1) and a source connected to a first power supply (VC); a second transistor (P22) of the first conductivity type having a gate connected to said first and second dummy column lines (RBL1, RBL21) and a source connected to said first power supply (VC); a first transistor (N21) of a second conductivity type having a drain connected to the drain of said first transistor (P21), a source connected to a second power supply (Vs), and a gate connected to the drain of said second transistor (P22); and a second transistor (N22) of the second conductivity type having a drain and a gate connected to the drain of said second transistor (P22), and a source connected to the second power supply (Vs). said second data sense circuit (SA2) comprises: a third transistor (P23) of a first conductivity type having a gate connected to said column line (L1) and a source connected to a first power supply (VC); a fourth transistor (P24) of the first conductivity type having a gate connected to said third and fourth dummy column lines (RBL22, RBL31) and a source connected to said first power supply (VC); a third transistor (N23) of a second conductivity type having a drain connected to the drain of said third transistor (P23), a source connected to a second power supply (Vs), and a gate connected to the drain of said fourth transistor (P24); and a fourth transistor (N24) of the second conductivity type having a drain and a gate connected to the drain of said fourth transistor (P24), and a source connected to the second power supply (Vs), and said third data sense circuit (SA3) comprises: a fifth transistor (P25) of a first conductivity type having a gate connected to said column line (L1) and a source connected to a first power supply (VC); a sixth transistor (P26) of the first conductivity type having a gate connected to said fifth and sixth dummy column lines (RBL32, RBL4) and a source connected to said first power supply (VC); a fifth transistor (N25) of a second conductivity type having a drain connected to the drain of said fifth transistor (P25), a source connected to a second power supply (Vs), and a gate connected to the drain of said sixth transistor (P26); and a sixth transistor (N26) of the second conductivity type having a drain and a gate connected to the drain of said fifth transistor (P25), and a source connected to the second power supply (Vs).

Claim 11

The device according to claim 9, further comprising discharging means (110, 111, 116, 117) connected between a second power supply (Vs) and each of said first to sixth dummy column lines and said column line, for discharging each of said first to sixth dummy column lines and said column line, wherein a voltage supplied from said second power supply is lower than a voltage supplied from said first power supply.

Claim 12

The device according to claim 9, further comprising charging means (120, 121, 126, 127) connected between said first power supply (Vc) and each of said first to sixth dummy column lines and said column line, for charging each of said first to sixth dummy column lines and said column line.

Claim 13

A semiconductor memory device characterized by comprising: row lines (WL1 to WLn); a plurality of memory cells (MC) each having a current path, a power supply voltage being supplied to one end of the current path, said memory cell being selectively driven by the associated one of said row lines, each memory cell having one of four threshold voltages and storing data of two bits; a column line (BL1 to BLn, L1) connected to the other end of the current path of each of the memory cells (MC); discharging means (74), connected to said column line, for discharging the column line for a predetermined time period; a plurality of sense amplifiers (SA1 to SA3), connected to said column line, for sensing the potential of the column line charged by a selected one of the memory cells, when said discharging means has completed a discharging operation; and a logic circuit (86), connected to output terminals of said sense amplifiers, for outputting the data of two bits stored in said memory cells.

Claim 14

The device according to claim 13, characterized in that said plurality of sense amplifiers (SA1 to SA3) comprise first to third sense amplifiers.

Claim 15

The device according to claim 14, characterized in that said first sense amplifier includes a first sense circuit, said first sense amplifier (SA1) includes a first sense circuit (100, 101), which is supplied with a potential of the column line, and which has a first threshold voltage, said second sense amplifier (SA2) includes a second sense circuit (102, 103), which is supplied with a potential of the column line, and which has a second threshold voltage higher than a first threshold voltage, and said third sense amplifier (SA3) includes a third sense circuit (104, 105), which is supplied with a potential of the column line, and which has a third threshold voltage higher than a second threshold voltage.