EP0642167A2
Expired / Lapsed
EP
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Semiconductor device having capacitor and manufacturing method thereof
Assignee: Panasonic Holdings Corp
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Filing: 1994-08-03
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Granted: —
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Expires: 2014-08-03
Abstract
Abstract A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm<3> or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10<2><1> atoms/cm<3> or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer. <IMAGE>
Inventors
- 👤 Koji Arita
- 👤 Eiji Fujii
- 👤 Yasuhiro Shimada
- 👤 Yasuhiro Uemoto
- 👤 Atsuo Inoue
- 👤 Toru Nasu
- 👤 Akihiro Matsuda
- 👤 Yoshihisa Nagano
- 👤 Taketoshi Matsuura
- 👤 Tatsuo Otsuki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 02:11
CPC Classifications
H; H10; H10D; H10D84/00; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B51/00; H10B51/30; H10B53/00; H10D1/00; H10D1/60; H10D1/68; H10D1/682; H10D1/692; H10D1/696; Y; Y10; Y10S; Y10S438/00; Y10S438/958
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
121 words
A semiconductor device comprising an integrated circuit and a capacitor formed on the integrated circuit, wherein the capacitor comprises a bottom electrode composed of a conductive layer formed on an insulating layer of the integrated circuit, a capacitor dielectric layer composed of one of a ferroelectric layer and high a dielectric layer formed on the bottom electrode, and a top electrode composed of a conductive layer formed on the capacitor dielectric layer, the top electrode and bottom electrode of the capacitor are connected with interconnections of the integrated circuit through contact holes provided in an interlayer insulating layer formed so as to cover the capacitor, and the moisture content of the interlayer insulating layer is 0.5g or less per 1 cm³.
Claim 2
Dependent Claim
129 words
A semiconductor device comprising an integrated circuit and a capacitor formed on the integrated circuit, wherein the capacitor comprises a bottom electrode composed of a conductive layer formed on an insulating layer of the integrated circuit, a capacitor dielectric layer composed of one of a ferroelectric layer and a high dielectric layer formed on the bottom electrode, and a top electrode composed of a conductive layer formed on the capacitor dielectric layer, the top electrode and bottom electrode of the capacitor are connected with interconnections of the integrated circuit through contact holes provided in an interlayer insulating layer formed so as to cover the capacitor, and a passivation layer formed to cover the interconnections is a silicon nitride layer with the hydrogen atom content of 10²¹ atoms/cm³ or less.
Claim 3
Dependent Claim
17 words
A semiconductor device of claim 2, wherein other passivation layer is formed on the silicon nitride layer.
Claim 4
Dependent Claim
18 words
A semiconductor device of claim 2, wherein a silicon oxide layer is formed beneath the silicon nitride layer.
Claim 5
Dependent Claim
135 words
A semiconductor device comprising an integrated circuit and a capacitor formed on the integrated circuit, wherein the capacitor comprises a bottom electrode composed of a conductive layer formed on an insulating layer of the integrated circuit, a capacitor dielectric layer composed of one of a ferroelectric layer and a high dielectric layer formed on the bottom electrode, and a top electrode composed of a conductive layer formed on the capacitor dielectric layer, the top electrode and bottom electrode of the capacitor are connected with interconnections of the integrated circuit through contact holes provided in an interlayer insulating layer formed so as to cover the capacitor, and a passivation layer is formed to cover the interconnections, and the passivation layer is composed of a phospho-silicate layer and a non-doped silicate layer sequentially from the interconnection side.
Claim 6
Dependent Claim
34 words
A semiconductor device of claim 5, wherein a second interlayer insulating layer possessing an opening at least in the part corresponding to the top electrode of the capacitor is provided beneath the passivation layer.
Claim 7
Dependent Claim
139 words
A semiconductor device comprising an integrated circuit and a capacitor formed on the integrated circuit, wherein the capacitor comprises a bottom electrode composed of a conductive layer formed on an insulating layer of the integrated circuit, a capacitor dielectric layer composed of one of a ferroelectric layer and a high dielectric layer formed on the bottom electrode, and a top electrode composed of a conductive layer formed on the capacitor dielectric layer, the top electrode and bottom electrode of the capacitor are connected with interconnections of the integrated circuit through contact holes provided in an interlayer insulating layer formed so as to cover the capacitor, a passivation layer is formed to cover the interconnections, and the top surface of the capacitor is covered with at least one of titanium nitride layer and titanium-tungsten layer through the interlayer insulating layer.
Claim 8
Dependent Claim
31 words
A semiconductor device of claim 7, wherein a silicon nitride layer possessing an opening in the part corresponding to the top electrode of the capacitor is provided beneath the passivation layer.
Claim 9
Dependent Claim
153 words
A manufacturing method of semiconductor device comprising: a step of forming a capacitor comprising a bottom electrode composed of a conductive layer, a capacitor dielectric layer composed of one of a ferroelectric layer and a high dielectric layer formed on the bottom electrode, and a top electrode composed of a conductive layer formed on the capacitor diele ctric layer, on an insulating layer of a semiconductor substrate in which an integrated circuit is fabricated, a step of forming an interlayer insulating layer by covering the capacitor , a step of heating the interlayer insulating layer, a step of forming contact holes reaching the integrated circuit, and top electrode and bottom electrode of the capacitor, through the insulating layer and interlayer insulating layer, a step of forming interconnections to be electrically connected with the integrated circuit and capacitor through the contact holes, and a step of forming a passivation layer by covering the interconnections.
Claim 10
Dependent Claim
41 words
A manufacturing method of semiconductor device of claim 9, wherein the heat treatment of the interlayer insulating layer is performed at a temperature between from 350°C to a temperature which gives rise to deterioration of a characteristic of the integrated circuit.
Claim 11
Dependent Claim
160 words
A manufacturing method of semiconductor device comprising: a step of forming a capacitor comprising a bottom electrode composed of a conductive layer, a capacitor dielectric layer composed of one of a ferroelectric layer and a high dielectric layer formed on the bottom electrode, and a top electrode composed of a conductive layer formed on the capacitor diele ctric layer, on an insulating layer of a semiconductor substrate in which an int egrated circuit is fabricated, a step of forming an interlayer insulating layer by covering the capacitor, a step of forming contact holes reaching the integrated circuit, and top electrode and bottom electrode of the capacitor, through the insulating layer and interlayer insulating layer, a step of forming interconnections to be electrically connected with the integrated circuit and capacitor through the contact holes, and a step of forming a passivation layer composed of a silicon nitride layer with hydrogen atom content of 10²¹ atoms/cm³ or less by covering the interconnections.
Claim 12
Dependent Claim
21 words
A manufacturing method of semiconductor device of claim 11, wherein the step for forming the passivation layer is by sputtering deposition.
Claim 13
Dependent Claim
35 words
A manufacturing method of semiconductor device of claim 12 wherein the step of forming the passivation layer is followed by the step of forming a second silicon nitride layer by plasma chemical vapor deposition method.
Claim 14
Dependent Claim
28 words
A manufacturing method of semiconductor device of claim 12, wherein the step of forming the passivation layer is preceded by a step of forming a silicon oxide layer.
Claim 15
Dependent Claim
22 words
A manufacturing method of semiconductor device of claim 14, wherein the silicon oxide layer contains at least one of boron and phosphorus.
Claim 16
Dependent Claim
152 words
A manufacturing method of semiconductor device comprising: a step of forming a capacitor comprising a bottom electrode composed of a conductive layer, a capacitor dielectric layer composed of one of a ferroelectric layer and a high dielectric layer formed on the bottom electrode, and a top electrode composed of a conductive layer formed on the capacitor dielectric layer, on an insulating layer of a semiconductor substrate in which an integrated circuit is fabricated, a step of forming an interlayer insulating layer by covering the capacitor, a step of forming contact holes reaching the integrated circuit, and top electrode and bottom electrode of the capacitor, through the insulating layer and interlayer insulating layer, a step of forming interconnections to be electrically connected with the integrated circuit and capacitor through the contact holes, and a step of sequentially forming a layer composed of phospho-silicate layer and a non-doped silicate layer by covering the interconnections.
Claim 17
Dependent Claim
50 words
A manufacturing method of semiconductor device of claim 16, wherein the step of forming the passivation layer is preceded by a step of forming a second interlayer insulating layer, and a step of removing the second interlayer insulating layer in the upper part of the top electrode of the capacitor.
Claim 18
Dependent Claim
49 words
A manufacturing method of semiconductor device of claim 17, wherein the step of forming the second interlayer insulating layer is for forming a silicon nitride layer by plasma CVD, and a step of heating the capacit or is added after the step of removing the second interlayer insulating layer.
Claim 19
Dependent Claim
40 words
A manufacturing method of semiconductor device of claim 18, wherein the heat treatment step of the capacitor consists of a first step of heating in inert gas or in vacuum, and a second step of heating in gas containing oxygen.
Claim 20
Dependent Claim
190 words
A manufacturing method of semiconductor device comprising: a step of forming a capacitor comprising a bottom electrode composed of a conductive layer, a capacitor dielectric layer composed of one of a ferroelectric layer and a high dielectric layer formed on the bottom electrode, and a top electrode composed of a conductive layer formed on the capacitor dielectric layer, on an insulating layer of a semiconductor substrate in which an integrated circuit is fabricated, a step of forming an interlayer insulating layer by covering the capacitor, a step of forming contact holes reaching the integrated circuit, and top electrode and bottom electrode of the capacitor, through the insulating layer and interlayer insulating layer, a step of forming interconnections to be electrically connected with the integrated circuit and capacitor through the contact holes, a step of forming a passivation layer by covering the interconnections, a step of removing only the passivation layer above the top electrode of the capacitor or both the interlayer insulating layer and passivation layer, a step of heating the capacitor, and a step of forming a second passivation layer by covering the upper part of the top electrode.
Claim 21
Dependent Claim
40 words
A manufacturing method of semiconductor device of claim 20, wherein the heat treatment step of the capacitor consists of a first step of heating in inert gas or in vacuum, and a second step of heating in gas containing oxygen.
Claim 22
Dependent Claim
161 words
A manufacturing method of semiconductor device comprising: a step of forming a capacitor comprising a bottom electrode composed of a conductive layer, a capacitor dielectric layer composed of one of a ferroelectric layer and a high dielectric layer formed on the bottom electrode, and a top electrode composed of a conductive layer formed on the capacitor dielectric layer, on an insulating layer of a semiconductor substrate in which an integrated circuit is fabricated, a step of forming an interlayer insulating layer by covering the capacitor, a step of forming contact holes reaching the integrated circuit, and top electrode and bottom electrode of the capacitor, through the insulating layer and interlayer insulating layer, a step of forming interconnections to be electrically connected with the integrated circuit and capacitor through the contact holes, and a step of forming a passivation layer by covering the interconnections, wherein a step of heating the capacitor is provided before or after the step of forming the interconnections.
Claim 23
Dependent Claim
40 words
A manufacturing method of semiconductor device of claim 22, wherein the heat treatment step of the capacitor consists of a first step of heating in inert gas or in vacuum, and a second step of heating in gas containing oxygen.
References Cited (Backward Citations)
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