Disc data reproducing apparatus and signal processing circuit

Claim 2

The apparatus according to claim 1, further comprising: means for detecting the frequency of the first clock in accordance with an externally supplied constant clock; and means for determining the demodulated data as invalid when the detected frequency is out of a predetermined range.

Claim 3

Apparatus for reproducing data stored on a disc, comprising: means for rotating the disc; pickup means for reading out data from the disc during rotation thereof; means for generating a digitized signal by quantizing the read out disc data in accordance with rotation of the disc; means for generating a first clock in response to the digitized signal; means for demodulating the digitized signal in response to the first clock and for outputting demodulated data; means for storing the demodulated data; means for deriving a second clock from the first clock and for outputting the second clock; means for supplying a constant clock at a predetermined frequency; means for selecting one of the second clock and the constant clock and for outputting the selected clock as a reference clock; and memory controlling means for controlling a writing operation to the storing means in response to the first clock and for controlling a reading operation from the storing means in response to the reference clock.

Claim 4

The apparatus according to claim 3, further comprising: means for detecting the frequency of the first clock in accordance with the the constant clock; and means for determining the demodulated data as invalid when the detected frequency is out of a predetermined range.

Claim 5

The apparatus according to claim 2 or 4 wherein the determining means including: means for storing the predetermined range.

Claim 6

The apparatus according to claim 1 or 2 wherein the deriving means comprising: derivation controlling means for controlling a derivation of the second clock by the deriving means.

Claim 7

The apparatus according to claim 6 wherein the derivation controlling means controls the derivation of the second clock according to an amount of data stored in the storing means so.

Claim 8

The apparatus according to claim 7 wherein the deriving means derives the second clock by a thinning-out process of the first clock, and the derivation controlling means increases a thinning-out amount when the amount of the data is less than a first predetermined value, and the derivation controlling means decreases the thinning-out amount when the amount of the data is larger than a second predetermined value.

Claim 9

The apparatus according to claim 7 wherein the amount of data stored in the storing means is represented by a difference between current read and write addresses of the storing means.

Claim 10

The apparatus according to claim 9, further comprising: first dividing means for dividing the first clock to generate a first frame clock; and second dividing means for dividing the reference clock to generate a second frame clock; wherein the derivation controlling means includes: first counter means for counting frames in the first frame clock as a first result; second counting means for counting frames in the second frame clock as a second result; and means for calculating a difference between the first and second results.

Claim 11

Apparatus for reproducing a plurality of data stored on a disc, the plurality of disc data capable of being classified into at least a first type data and a second type data, the apparatus comprising: means for designating information data to be read among the plurality of disc data and for designating one of the first and second types of data; a disc motor for rotating the disc; a pickup for reading disc data designated by the designating means; a first clock generator to generate a first clock responsive to the disc data read from the disc; a second clock deriving circuit for deriving a second clock from the first clock; an oscillator for supplying a constant clock at a predetermined frequency; a selector for selecting one of the second clock and the constant clock and for outputting the selected clock as a reference clock; a first divider for dividing the first clock to generate a first frame clock; and a second divider for dividing the reference clock to generate a second frame clock; a buffer memory for storing disc data read from the disc; and memory controlling means for controlling a writing operation to the buffer memory in response to the first frame clock and for controlling a reading operation from the buffer memory in response to the second frame clock; wherein, when the designated disc data is the first type data, the selector selects the second clock as the reference clock, and when the designated disc data is the second type data, the selector selects the constant clock as the reference clock.

Claim 12

The apparatus according to claim 11 wherein the first type data includes ROM data and the second type data includes audio data.

Claim 13

The apparatus according to claim 11 wherein the second clock deriving circuit comprises: a derivation controlling circuit for controlling a derivation of the second clock by the second clock deriving circuit according to an amount of data stored in the buffer memory when the designated disc data is the first type data, the second clock deriving circuit deriving the second clock by a thinning-out process of the first clock, the derivation controlling circuit increasing a thinning-out amount when the amount of stored data is less than a first predetermined value, and the derivation controlling circuit decreasing the thinning-out amount when the amount of stored data is larger than a second predetermined value, so that a frequency of the second clock is controlled in accordance with the amount of stored data.

Claim 14

The apparatus according to claim 13, further comprising: a detector to detect a frequency of the first clock in accordance with the constant clock; and a determining circuit to determine the demodulated data as invalid when the detected frequency is out of a predetermined range.

Claim 15

The apparatus according to claim 14 wherein the determining means including: means for storing the predetermined range.

Claim 16

A signal processing circuit for use in processing data read from a rotating disc for storage in a buffer memory, comprising: a first clock generating circuit to generate a first clock responsive to an EFM signal generated by quantizing the data read from the rotating disc; a demodulator to demodulate the EFM signal in response to the first clock and to output demodulated data; a second clock deriving circuit to derive a second clock from the first clock and to output the second clock as a reference clock; and a memory controlling circuit to control writing of the demodulated data to the buffer memory in response to the first clock and for controlling reading of the demodulated data from the buffer memory in response to the reference clock.

Claim 17

The signal processing circuit according to claim 16, further comprising: a first detector to detect a frequency of the first clock in accordance with an externally supplied constant clock; and a determining circuit to determine the demodulated data as invalid when the frequency is out of a predetermined range.

Claim 18

A signal processing circuit for use in processing data read from a rotating disc for storage in a buffer memory, comprising: a first clock generating circuit to generate a first clock responsive to an EFM signal generated by quantizing the data read from the rotating disc; a demodulator to demodulate the EFM signal in response to the first clock and to output demodulated data; a second clock deriving circuit to derive a second clock from the first clock and to output the second clock; a selector to select one of the second clock and an externally supplied constant clock at a predetermined frequency, and for outputting the selected clock as a reference clock; and a memory controlling circuit to control writing of the demodulated data to the buffer memory in response to the first clock and for controlling reading of the demodulated data from the buffer memory in response to the reference clock.

Claim 19

The signal processing circuit according to claim 16 or 18, further comprising the buffer memory.

Claim 20

The signal processing circuit according to claim 18 wherein the deriving circuit comprises: a derivation controller to control a derivation of the second clock by the deriving circuit.

Claim 21

The signal processing circuit according to claim 20 wherein the derivation controller controls the derivation of the second clock according to an amount of data stored in the buffer memory so that a frequency of the second clock is controlled in accordance with the amount of store data.

Claim 22

The signal processing circuit according to claim 21 wherein the deriving circuit derives the second clock by a thinning-out process of the first clock, and the derivation controller increases a thinning-out amount when the amount of stored data is less than a first predetermined value, and the derivation controller decreases the thinning-out amount when the amount of stored data is larger than a second predetermined value.

Claim 23

The apparatus according to claim 21 or 22 wherein the amount of stored data is represented by a difference between current read and write addresses of the buffer memory.

Claim 24

The signal processing circuit according to claim 23, further comprising: a first divider to divide the first clock to generate a first frame clock; and a second divider to divide the reference clock to generate a second frame clock, wherein the derivation controller includes: a first counter to count up frames in the first frame clock as a first result; a second counter for count up frames in the second frame clock as a second result; and a subtractor to calculate a difference between the first and second results.

Claim 25

The signal processing circuit according to claim 24 wherein the second divider outputs at least one intermediate clock distinct from the second frame clock.

Claim 26

The signal processing circuit according to claim 25, further comprising: a digital/analog converter interface circuit with a intermediate clock output terminal for receipt of the intermediate clock.

Claim 27

The signal processing circuit according to claim 18, further comprising: a detector to detect a frequency of the first clock in accordance with the constant clock; and determining circuit to determine the demodulated data as invalid when the frequency is out of a predetermined range.

Claim 28

The signal processing circuit according to claim 27 wherein the determining circuit including: a first and second registers to holding the predetermined range.

Claim 31

Apparatus for reproducing data stored on a disc, comprising: means for rotating the disc; pickup means for reading out disc data from the disc during rotation thereof; means for generating a digitized signal by quantizing the read out disc data in accordance with rotation of the disc; means for generating a reproduction reference clock responsive to the digitized signal; means for supplying an oscillator clock at a predetermined frequency; means for demodulating the digitized signal in response to the first clock and for outputting demodulated data; means for storing the demodulated data; memory controlling means for controlling a writing operation to the storing means in response to the reproduction reference clock; means for detecting the frequency of the reproduction reference clock in accordance with the constant clock, and means for determining the demodulated data as invalid when the detected frequency is out of a predetermined range.

Claim 32

The apparatus according to claim 31 wherein the memory controlling means includes means for controlling a reading operation from the storing means in response to a read-out reference clock, wherein a frequency of the read-out reference clock changes in accordance with the rotation of the disc.

Claim 33

The apparatus according to claim 32 wherein the determining means including: means for storing the predetermined range.

Claim 34

A signal processing circuit for use in processing information data read from a rotating disc, for storage in a buffer memory comprising: a clock generating circuit to generate a first clock responsive to an EFM signal generated by quantizing the information data in accordance with a disc rotation; a demodulator to demodulate the EFM signal in response to the first clock and to output demodulated data; a second clock generating circuit to generate a second clock and to output the second clock as a reference clock; and memory controlling circuit to control writing the demodulated data to the buffer memory in response to the first clock and to control reading the demodulated data from the buffer memory in response to the reference clock; a second detector to detect a frequency of the first reference clock in accordance with a constant clock; and a determining circuit to determine the demodulated data as invalid when the detected frequency is out of a predetermined range.

Claim 35

The signal processing circuit according to claim 34 wherein the reference clock changes in accordance with the disc rotation.

Claim 36

The signal processing circuit according to claim 35, further comprises the buffer memory.

Claim 37

The signal processing circuit according to claim 36 wherein the determining circuit including: a first and second registers to holding the predetermined range.

Claim 38

A reproduction speed detecting circuit for use in processing data read from a rotating disc, the processing including generating a reproduction reference clock responsive to an EFM signal obtained by quantizing the information data, comprising: a first divider for dividing the reproduction reference clock to generate a first clock; a second divider for dividing a constant clock to generate a second clock; a timing pulse generator to generate a latch pulse and a clear pulse in response to a detection of a falling edge of the second clock; a counter to count up the first clock, the counter being reset by the clear pulse, and an output circuit to output a value of the counter in response to the latch pulse.

Claim 39

The reproduction speed detecting circuit according to claim 38 wherein the output circuit comprises: an encoder to encode an output of the counter to decrease a bit-width thereof; and a latch circuit to latch an output of the encoder in response to the latch pulse.