Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
168 words
An apparatus for the parallel decoding of encoded image signals supplied in the form of an encoded bit stream separated in variable length encoded blocks, said apparatus comprising: a circuit having a single input terminal and N output terminals for receiving the encoded bit stream through the single input terminal, and demultiplexing said blocks in the encoded bit stream over the N output terminals; N parallel processing paths, each including a buffer memory for respectively performing decoding operation including variable length decoding on said blocks provided in its buffer memory; and a provisional buffer memory circuit connected between the N output terminals and the N buffer memories for temporarily storing said blocks to be applied to a respective one of the N buffer memories when said respective one of the N buffer memories is in a buffer full state, and providing said blocks to said respective one of the N buffer memories as said respective one of the buffer memories has been released from the buffer full state.
Claim 2
Dependent Claim
26 words
The parallel decoding apparatus of claim 1, further comprising a circuit for multiplexing output signals from the N parallel processing paths into a single data stream.
Claim 3
Dependent Claim
37 words
The parallel decoding apparatus of claim 2, wherein each of the N parallel processing paths further includes a variable length decoding circuit, an inverse quantization circuit, an inverse normalization circuit and an inverse discrete cosine transform circuit.
Claim 4
Dependent Claim
175 words
The parallel decoding apparatus of claim 1, wherein said provisional buffer memory circuit includes: 1) a provisional buffer memory operating in a first-in-first-out manner; and 2) N routing circuits connected between the N output terminals and the N buffer memories, each routing circuit having: a) input routing means for receiving said blocks from a respective one of the N output terminals and then providing said presently received blocks either to said provisional buffer memory for storage therein when a respective one of the N buffer memories is in a buffer full state or when there exist said blocks previously received from the respective one of the N output terminals and currently stored in the provisional buffer memory, or to the respective one of the N buffer memories otherwise; and b) output selecting means for connecting the respective one of the N buffer memories either with the provisional buffer memory when there exist said presently received blocks or said previously received blocks currently stored in the provisional buffer memory, or with the input routing means otherwise.
Claim 5
Dependent Claim
68 words
The parallel decoding apparatus of claim 4, wherein said provisional buffer memory has a storage capacity of, at most, NC, and each of the N buffer memories has a storage capacity less than said NC, wherein said NC represents the minimum storage capacity of an equivalent decoding apparatus having a serial structure, which is to operated at the same operating frequency as that of the parallel decoding apparatus.
Claim 6
Dependent Claim
175 words
The parallel decoding apparatus of claim 3, wherein said provisional buffer memory circuit includes: 1) a provisional buffer memory operating in a first-in-first-out manner; and 2) N routing circuits connected between the N output terminals and the N buffer memories, each routing circuit having: a) input routing means for receiving said blocks from a respective one of the N output terminals and then providing said presently received blocks either to said provisional buffer memory for storage therein when a respective one of the N buffer memories is in a buffer full state or when there exist said blocks previously received from the respective one of the N output terminals and currently stored in the provisional buffer memory, or to the respective one of the N buffer memories otherwise; and b) output selecting means for connecting the respective one of the N buffer memories either with the provisional buffer memory when there exist said presently received blocks or said previously received blocks currently stored in the provisional buffer memory, or with the input routing means otherwise.
Claim 7
Dependent Claim
68 words
The parallel decoding apparatus of claim 6, wherein said provisional buffer memory has a storage capacity of, at most, NC, and each of the N buffer memories has a storage capacity less than said NC, wherein said NC represents the minimum storage capacity of an equivalent decoding apparatus having a serial structure, which is to operated at the same operating frequency as that of the parallel decoding apparatus.