EP0629068A1
Expired / Lapsed
EP
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4B6B coding scheme
Assignee: STMicroelectronics Ltd
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Filing: 1994-06-08
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Granted: —
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Expires: 2014-06-08
Abstract
Abstract An encoding scheme relies on a d.c. balanced code wherein each message to be transmitted is sent as a plurality of symbols, each symbol having six bits, three ones and three zeros. Out of the twenty combinations of balanced six-bit codes, two codes are reserved to operate as control tokens, being 010101 and 101010. Because of the particular format of the symbols, control tokens can be easily detected. Furthermore, they can be combined in longer bit sequences for use as initialisation and disconnect sequences.
Inventors
- 👤 Christopher Paul Hulme Walker
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 20:43
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/004; H04L1/0056; H04L1/0057; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0602; H04J3/0605; H04J3/062; H04J3/0632; H04L1/0078; H04L1/0083; H04L1/24; H04L1/245; H04L1/246; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4906; H04L25/4908; H04L7/00; H04L7/04; H04L7/041; H04L7/046
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
98 words
A method of generating control tokens in a message transmission system wherein each message includes at least one data token comprising a plurality of four bit values and at least one terminator token in a first format, the method comprising: encoding each four bit value into a second format as a six bit symbol having three ones and three zeros, each symbol being selected out of a set of sixteen symbols assigned exclusively as data symbols and excluding the symbols 010101 and 101010, and generating control tokens in the second format using the control symbols 010101 and 101010.
Claim 2
Dependent Claim
76 words
A method according to claim 1 wherein a first type of the control symbols is allocated so that its first bit matches the last bit of a preceding symbol and a second type of the control symbols is allocated so that its first bit is the logical inverse of the last bit of a preceding symbol, the method comprising: combining the first and second types of control symbols to produce a plurality of different control tokens.
Claim 3
Dependent Claim
19 words
A method according to claim 2 wherein each control token commences with a control symbol of the first type.
Claim 4
Dependent Claim
63 words
A method according to claim 2 or 3 wherein each message comprises at least one packet in the first format, each packet including at least one data token and a terminator token in the form of an end of packet control token, and wherein the end of packet control token comprises a control symbol of the first type followed by a data symbol.
Claim 5
Dependent Claim
40 words
A method according to claim 2 or 3 wherein each message includes as a terminator token an end of message control token which in the second format comprises a data symbol followed by a control symbol of the first type.
Claim 6
Dependent Claim
41 words
A method according to claim 2 or 3 wherein a flow control token for controlling the quantity of data symbols transmitted between two devices comprises a control symbol of the first type followed by another control symbol of the first type.
Claim 7
Dependent Claim
40 words
A method according to claim 2 or 3 wherein an idle token for transmission when there are no data symbols to be transmitted comprises a control symbol of the first type followed by a control symbol of the second type.
Claim 8
Dependent Claim
40 words
A method according to claim 2 or 3 wherein an initialise token comprises a control symbol of the first type followed by three control symbols of the second type in succession thereby to provide a sequence of 24 alternating bits.
Claim 9
Dependent Claim
90 words
Data transmission circuitry comprising: input means for receiving messages in a first format including data tokens represented by four bit values and terminator tokens; encoding circuitry for encoding each four bit value as a six bit symbol having three ones and three zeros, each symbol being selected out of a set of sixteen symbols uniquely assigned as data symbols and excluding the symbols 010101 and 101010 and for generating control tokens using the symbols 010101 and 101010; and output means for transmitting the encoded data symbols and generated control tokens.
Claim 10
Dependent Claim
64 words
Data transmission circuitry according to claim 9 wherein the input means comprises a buffer arranged to receive bits of an incoming token in parallel, the encoding means providing for each incoming token two six bit symbols and outputting the bits of these symbols in parallel and the output means comprising a parallel to serial converter for transmitting the bits of the encoded symbols serially.
Claim 11
Dependent Claim
49 words
Data transmission circuitry according to claim 10 in which the output means includes circuitry capable of outputting selectively one of two terminator tokens, a first terminator token being a control symbol followed by a data symbol and a second terminator being a data symbol followed by a control symbol.
Claim 12
Dependent Claim
121 words
Data receiving circuitry including a synchronisation detection circuit comprising; a clock generator connected to receive an incoming stream of bits and to generate therefrom a bit clock having a clock edge defining each bit position in the bit stream; a counter arranged to receive the incoming bit stream and the bit clock and to count the number of successive transitions in the incoming bit stream and to provide a first output signal when the count is twelve; a clock divider for dividing the bit clock by twelve to produce a second output signal every twelfth clock edge; and phase detecting means for comparing said first and second output signals and for providing an error signal when they are out of phase.
Claim 13
Dependent Claim
55 words
Data receiving circuitry according to claim 11 wherein the synchronisation detection circuit can also comprise an initialisation detector in the form of a second counter arranged to receive said bit stream and said bit clock and to provide a start signal on counting twenty-three successive transitions said start signal being supplied to said first counter.
Claim 14
Dependent Claim
68 words
Data receiving circuitry according to claim 12 which comprises: input means for receiving messages in the form of a sequence of pairs of six bit symbols; decoding circuitry for decoding each pair of six bit symbols into data tokens or terminator tokens depending on whether the pair of symbols includes a control symbol being 010101 or 101010; and output means for transmitting the data tokens or terminator tokens.
Claim 15
Dependent Claim
44 words
Data receiving circuitry according to claim 14 wherein the decoding circuitry is capable of generating a first terminator token when a control symbol is followed by a data symbol and a second terminator token when a data symbol is followed by a control symbol.
Claim 16
Dependent Claim
25 words
An interface comprising data transmission circuitry according to claim 9, 10 or 11 and data receiving circuitry according to claim 11, 12, 13 or 14.
References Cited (Backward Citations)
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