EP0628831B1
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EP
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Bidirectional boundary scan test cell
Assignee: Texas Instruments Inc
•
Filing: 1989-08-23
•
Granted: 1998-03-18
•
Expires: 2009-08-23
Abstract
No abstract record available.
Inventors
- 👤 Lee D. Whetsel, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 13:12
CPC Classifications
G; G11; G11C; G11C29/00; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318541; G01R31/318555
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
312 words
A boundary scan test cell for to be located at the boundary of an internal application logic comprising first (24) and second (26) memories and first (22,34)
and second (28) multiplexers each having an output and at
least two inputs, wherein a first one and a second one of the inputs to
the first multiplexer (22,34) are connected to a serial data input
terminal (SDI), and a first circuit data input terminal (DINB)
respectively, the input of the first memory (24) is connected to the
output of the first multiplexer (22,34) the output of the first memory (24) is connected to the
input of the second memory (26) and to a serial data output (SDO) terminal, and first and second ones of the inputs of the second
multiplexer (28) are connected to the output of the second
memory (26) and to the first circuit data terminal (DINB)
respectively, characterised in that the boundary scan test cell is
bidirectional, whereby the boundary scan test cell may be
used in connection with an input/output
pin (40), through which signals may flow
in both directions, the first multiplexer (22,34) having a third
input connected to a second circuit data input terminal (DINA) for receiving an output from said internal
application logic, the
test cell further including a third multiplexer (36) having
an output (DOUTA) and at least two inputs, a first one and a
second one of the inputs of the third
multiplexer (36) being connected to the non-inverted output (LQ), of the
second memory (26) and to the second circuit data input terminal
(DINA) respectively, and in that a fourth input of the first multiplexer (22,34) is
connected to an inverted output of the second memory (26), and in that said input/output pin (40)
is connected to both said first circuit
data input terminal (DINB) and said
output (DOUTA) of said third multiplexer (36).
Claim 2
Dependent Claim
29 words
A bidirectional boundary scan test cell according to
claim 1, wherein a fifth input to the first multiplexer
(22,34) is connected to the output of the first memory (24).
Claim 3
Dependent Claim
75 words
A bidirectional boundary scan test cell according to
any one of claims 1 to 2, wherein the second and third
multiplexers are such that and are so connected to a common
control terminal (DMX) that, in use, they operate, in
response to a signal supplied to the control terminal, to
switch the outputs of the second and third multiplexers
between being both connected to their first inputs and being
both connected to their second inputs.
Claim 4
Dependent Claim
43 words
a bidirectional boundary scan test cell according to
any one of claims 1 to 3, connected to a bidirectional data
pin (40), wherein the pin is connected to both the output of
the third multiplexer (DOUTA) and the first circuit data
terminal (DINB).
Claim 5
Dependent Claim
29 words
A bidirectional boundary scan test cell according to
claim 4, wherein the connection of the output of the third
multiplexer to the pin is through a tristate buffer (38).
Claim 6
Dependent Claim
54 words
An integrated circuit comprising an application logic
circuit and boundary scan test cells, each according to any
one of claims 1 to 5, wherein the circuit data terminals, and
the outputs of the second, or second and third, multiplexers
are connected to the pins of the integrated circuit and to
the application logic circuit.
Claim 7
Dependent Claim
33 words
An integrated circuit according to claim 6, wherein the
first memories of a plurality of boundary scan test cells are
serially connected using the serial data terminals and the
outputs of those memories.
Claim 8
Dependent Claim
53 words
A use of a boundary scan test cell according to any one
of claims 1 to 5, in a load mode in which the first memory
receives data through the first multiplexer (22,34) from the
circuit data terminal to which the second, or second or
third, inputs of the first multiplexer is connected.
Claim 9
Dependent Claim
49 words
A use of a boundary scan test cell according to any one
of claims 1 to 5, in a shift mode, or a use according to
claim 8 further including use in such a shift mode, wherein
in the shift mode memory receives data from the serial data
terminal.
Claim 10
Dependent Claim
73 words
A use of a boundary scan test cell according to any one
of claims 1 to 5, in a toggle mode, or a use according to
claim 8 or claim 9 further including use in such a toggle
mode, wherein in the toggle mode the first memory (24)
receives data from the inverted output of the second memory
(26), the toggle mode being such that the first memory
toggles between two binary values.
Claim 11
Dependent Claim
54 words
A use of a boundary scan test cell according to claim 2
in an idle mode, or use of such a cell according
to any one of claims 8 to 10 further including use in such an
idle mode, wherein in the idle mode the first memory (24)
receives data from its own input.
Claim 12
Dependent Claim
40 words
A use of a boundary scan test cell according to any one
of claims 8 to 11, wherein the load, shift, toggle, or idle
mode is performed with the output of the second multiplexer
(28) connected to its second input.
Claim 13
Dependent Claim
49 words
A use of a boundary scan test cell according to any one
of claims 8 to 12, wherein the load, shift, or idle mode is
performed with the output of the second multiplexer (28)
connected to its first input while the output of the second
memory (26) is maintained.
Claim 14
Dependent Claim
36 words
A use of a boundary scan test cell according to any one
of claims 8 to 13, wherein the toggle mode is performed with
the output of the second multiplexer (28) connected to its
first input.
References Cited (Backward Citations)
No citation records indexed.
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