Semiconductor memory device

Claim 2

The semiconductor memory device of Claim 1 wherein said bit line consists of a pair of bit lines (first bit line and second bit line), further comprising a sense amplifier to which said first bit line and said second bit line are coupled.

Claim 3

The semiconductor memory device of Claim 2 wherein said adjusting capacitor consists of a pair of adjusting capacitors (first adjusting capacitor and second adjusting capacitor), said first adjusting capacitor being coupled to said first bit line, said second adjusting capacitor being coupled to said second bit line.

Claim 4

The semiconductor memory device of Claim 3 wherein said first adjusting capacitor and said second adjusting capacitor consist of a plurality of capacitors respectively.

Claim 5

The semiconductor memory device of Claim 4 wherein each of said plural number of capacitors has a capacitance value about equal to that of said ferroelectric capacitor.

Claim 6

The semiconductor memory device of Claim 4 wherein a separating means is provided between at least one of said plural number of capacitors and said bit line.

Claim 7

The semiconductor memory device of Claim 3 wherein said first adjusting capacitor and said second adjusting capactior comprise a ferroelectric film.

Claim 8

The semiconductor memory device of Claim 2 wherein said adjusting capacitor has a capacitance value decided in such a way that the potential difference between the reading potential of said first bit line and the reading potential of said second bit line is not less than the minimum operating voltage of said sense amplifier.

Claim 9

The semiconductor memory device of Claim 8 wherein said capacitance value is the minimal value.

Claim 10

The semiconductor memory device of Claim 1 wherein said adjusting capacitor comprises a ferroelectric film.

Claim 11

The semiconductor memory device of Claim 10 wherein the component system of the material of said ferroelectric film is identical to that of the material of said ferroelectric capacitor.

Claim 12

The semiconductor memory device of Claim 10 wherein the shape and the size of said adjusting capacitor are about the same as the shape and the size of said ferroelectric capacitor.

Claim 13

A semiconductor memory device comprising: a first bit line and a second bit line forming a pair, a word line, a plate electrode, a signal line, a ferroelectric capacitor having first electrode and second electrode, said second electrode being coupled to said plate electrode, a MOS transistor the source of which is coupled to the first electrode of said ferroelectric capacitor, the gate is coupled to said word line and the drain is coupled to said first bit line, a first adjusting capacitor coupled between said first bit line and said signal line, a second adjusting capacitor coupled to said second bit line, and a sense amplifier coupled to said first bit line and said second bit line.

Claim 14

The semiconductor memory device of Claim 13 wherein the logical voltage of the electrode on one side and the logical voltage of the electrode on the other side in said first adjusting capacitor are different from each other when said semiconductor memory device is on standby.

Claim 15

The semiconductor memory device of Claim 13 wherein the logical voltage of the electrode on one side and the logical voltage of the electrode on the other side in said first adjusting capacitor are both at "L" when said semiconductor memory device is on standby.

Claim 16

A semiconductor memory device comprising: a first bit line and a second bit line forming a pair, a first word line and a second word line forming a pair, a plate electrode, a signal line, a first ferroelectric capacitor and a second ferroelectric capacitor coupled to said plate electrode, a first MOS transistor the source of which is coupled to said first ferroelectric capacitor, the gate is coupled to said first word line and the drain is coupled to said first bit line, a second MOS transistor the source of which is coupled to said second ferroelectric capacitor, the gate is coupled to said second word line and the drain is coupled to said second bit line, a first adjusting capacitor coupled between said first bit line and said signal line, a second adjusting capacitor coupled between said second bit line and said signal line, and a sense amplifier coupled to said first bit line and said second bit line, the capacitance value of said second ferroelectric capacitor being found between the capacitance value of said first ferroelectric capacitor at the time when the logical voltage "H" is written in said first ferroelectric capacitor and the capacitance value of said first ferroelectric capacitor at the time when the logical voltage "L" is written in said first ferroelectric capacitor.

Claim 17

A semiconductor memory device of Claim 16 wherein said first adjusting capacitor and said second adjusting capacitor have respectively a capacitance value decided in such a way that the potential difference between the reading potential of said first bit line and the reading potential of said second bit line at the time when the logical voltage "H" or "L" is written in said first ferroelectric capacitor is not less than the mimimum operating voltage of said sense amplifier.

Claim 18

A semiconductor memory device comprising: a plurality of pairs of first bit line and second bit line arranged in columns, a plurality of word lines arranged in rows, a plurality of plate electrodes, a plurality of sense amplifiers coupled to said first bit line and said second bit line, a plurality of pairs of first adjusting capacitor coupled to said first bit line and second adjusting capacitor coupled to said second bit line, and a plurality of memory cells arranged in rows and columns, each memory cell comprising a first MOS transistor, a second MOS transistor, a first ferroelectric capacitor and a second ferroelectric capacitor, the drain of said first MOS transistor being coupled to said first bit line and the drain of said second MOS transistor being coupled to said second bit line respectively, the source of said first MOS transistor being coupled to the electrode on one side of said first ferroelectric capacitor and the source of said second MOS transistor being coupled to the electrode on one side of said second ferroelectric capacitor, the other electrode of said first ferroelectric capacitor and the other electrode of said second ferroelectric capacitor being coupled to said plate electrode.

Claim 19

A method for initializing said first adjusting capacitor and said second adjusting capacitor of the semiconductor memory device of Claim 7 comprising the steps of applying a logical voltage "L" to said first bit line and a logical voltage "H" to said second bit line, and applying a logical voltage "H" to said first bit line and a logical voltage "L" to said second bit line.

Claim 20

A method for initializing said first adjusting capacitor and said second adjusting capacitor of the semiconductor memory device of Claim 7 comprising the step of applying a logical voltage "H" to said first bit line and said second bit line.

Claim 21

A method for initializing said first adjusting capacitor and said second adjusting capacitor of the semiconductor memory device of Claim 15 comprising the steps of applying a logical voltage "L" to said first bit line and a logical voltage "H" to said second bit line, and applying a logical voltage "H" to said first bit line and a logical voltage "L" to said second bit line.

Claim 22

A method for initializing said first adjusting capacitor and said second adjusting capacitor of the semiconductor memory device of Claim 15 comprising the step of applying a logical voltage "H" to said first bit line and said second bit line.