EP0627682A1
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EP
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Floating-point processor for a high performance three dimensional graphics accelerator
Assignee: Sun Microsystems Inc
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Filing: 1994-04-11
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Granted: —
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Expires: 2014-04-11
Abstract
Abstract A floating-point processor for a high performance three dimensional graphics accelerator in a computer system is disclosed. The floating-point processor implements specialized graphics micro instructions. The specialized graphics micro instructions include a swap micro instruction which causes a hardware remapping of general purpose register groups to sort triangle vertices. The specialized graphics micro instructions also include specialized conditional branches for three dimensional geometry.
Inventors
- 👤 Michael F. Deering
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 21:04
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30145; G06F9/3016; G06F9/30167; G06T; G06T17/00; G06F9/38; G06F9/3877; G06F9/3879; G06T1/00; G06T1/20
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
192 words
A floating-point processor for a graphics accelerator, comprising: input circuit having a multiple buffer input register file, the input circuit receiving a reformatted geometry packet over a command to floating-point bus and buffering the reformatted geometry packet; output circuit having a multiple buffer output register file, the output circuit buffering an draw packet and transferring the draw packet over a command to draw bus; register file circuit having a general purpose register file including a first register group, a second register group and a third register group; control sequencer assembling the draw packet into the output register file by reading a plurality of specialized graphics micro instructions from a control store and executing the specialized graphics micro instructions using a set of function units, the specialized graphics micro instructions comprising a floating-point compare micro instruction and a swap micro instruction, the swap micro instruction rearranging a register map for the first, second, and third register groups according to a series of result flags corresponding to the floating-point compare micro instruction, such that a set of vertex values stored in the first, second, and third register groups are sorted in a predefined order.
Claim 2
Dependent Claim
39 words
The floating-point processor of claim 1, wherein the function units comprise a floating-point multiplier circuit, a floating point arithmetic logic unit circuit, a reciprocal circuit, a reciprocal square-root circuit, and an integer arithmetic logic unit circuit, a reciprocal circuit.
Claim 3
Dependent Claim
44 words
The floating-point processor of claim 1, wherein the general purpose register file comprises a predetermined number of general purpose registers, such that the predetermined number of general purpose registers provides data storage for the inner loops of commonly occurring three dimensional graphics processing algorithms.
Claim 4
Dependent Claim
54 words
The floating-point processor of claim 1, wherein the specialized graphics micro instructions further comprise a clip test micro instruction, the clip test micro instruction comparing a point to one or two clip planes according to a clip-mode bit of a state-bits register, and shifting one or two result bits into a clip bits register.
Claim 5
Dependent Claim
39 words
The floating-point processor of claim 4, wherein the specialized graphics micro instructions further comprise a plurality of geometry conditional branch instructions, each geometry conditional branch instruction determining a branch condition according to the contents of the clip bits register.
Claim 6
Dependent Claim
51 words
The floating-point processor of claim 5, wherein the specialized graphics micro instructions further comprise a micro instruction for converting a floating-point value to an integer value, a micro instruction for converting the integer value to the floating-point value, and a micro instruction for determining an absolute value of a data value.
Claim 7
Dependent Claim
19 words
The floating-point processor of claim 6, wherein the specialized graphics micro instructions further comprise a floating-point reciprocal micro instruction.
Claim 8
Dependent Claim
38 words
The floating-point processor of claim 7, wherein the specialized graphics micro instructions further comprise a block load instruction and a block store instruction for performing data block transfers between the control store and the general purpose register file.
Claim 9
Independent Claim
175 words
A method for performing floating-point processing functions for a graphics accelerator, comprising the steps of: receiving a reformatted geometry packet over a command to floating-point bus from a command preprocessor, and buffering the reformatted geometry packet in a multiple buffer input register file; generating an draw packet by reading a plurality of specialized graphics micro instructions from a control store and executing the specialized graphics micro instructions using a set of function units and a general purpose register file having a first register group, a second register group and a third register group, the specialized graphics micro instructions comprising a floating-point compare micro instruction and a swap micro instruction, the swap micro instruction rearranging a register map for the general purpose register file according to a series of result flags corresponding to the floating-point compare micro instruction, such that a set of vertex values stored in the first, second, and third register groups are sorted in a predefined order; broadcasting the draw packet over a command to draw bus to a plurality of draw processors.
Claim 10
Dependent Claim
38 words
The method of claim 9, wherein the function units comprise a floating-point multiplier circuit, a floating point arithmetic logic unit circuit, a reciprocal circuit, a reciprocal square-root circuit, and an integer arithmetic logic unit circuit, a reciprocal circuit.
Claim 11
Dependent Claim
41 words
The method of claim 9, wherein the general purpose register file comprises a predetermined number of general purpose registers, such that the predetermined number of general purpose registers provides data storage for the inner loops of three dimensional graphics processing algorithms.
Claim 12
Dependent Claim
53 words
The method of claim 9, wherein the specialized graphics micro instructions further comprise a clip test micro instruction, the clip test micro instruction comparing a point to one or two clip planes according to a clip-mode bit of a state-bits register, and shifting one or two result bits into a clip bits register.
Claim 13
Dependent Claim
38 words
The method of claim 12, wherein the specialized graphics micro instructions further comprise a plurality of geometry conditional branch instructions, each geometry conditional branch instruction determining a branch condition according to the contents of the clip bits register.
Claim 14
Dependent Claim
50 words
The method of claim 13, wherein the specialized graphics micro instructions further comprise a micro instruction for converting a floating-point value to an integer value, a micro instruction for converting the integer value to the floating-point value, and a micro instruction for determining an absolute value of a data value.
Claim 15
Dependent Claim
18 words
The method of claim 14, wherein the specialized graphics micro instructions further comprise a floating-point reciprocal micro instruction.
Claim 16
Dependent Claim
37 words
The method of claim 15, wherein the specialized graphics micro instructions further comprise a block load instruction and a block store instruction for performing data block transfers between the control store and the general purpose register file.
References Cited (Backward Citations)
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