EP0624952A2
Expired / Lapsed
EP
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Integrated circuit with a low-power mode and clock amplifier circuit for same
Assignee: Motorola Solutions Inc
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Filing: 1994-05-05
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Granted: —
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Expires: 2014-05-05
Abstract
Abstract An integrated circuit (40) has a low-power mode in which at least one switched inverter stage (60) of a clock amplifier (41) is disabled in response to a stop signal. The stop signal indicates that the integrated circuit (40) is in low-power mode. In one embodiment, each switched inverter stage is a complementary metal-oxide-semiconductor (CMOS) switched inverter (60), in which an additional P-channel transistor (61) is connected between the source of an inverter P-channel transistor (62) and a positive power supply voltage terminal, and in which an additional N-channel transistor (64) is connected between a source of an inverter N-channel transistor (63) and a negative power supply voltage terminal. A non-switched inverter stage (52) remains active during low-power mode to maintain a DC value of a clock input signal near a switchpoint of the clock amplifier (41). <IMAGE>
Inventors
- 👤 Ravi Shankar
- 👤 Kin Ki Ghau-Lee
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-24 07:44
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0008; H03K19/0013; H03K19/0016
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
212 words
An integrated circuit with a low-power mode (40), comprising: inverter means (51, 52) for receiving a clock signal and a stop signal, and for providing an output signal on an output terminal thereof in response to said clock signal, said inverter means (51, 52) including a switched inverter means (51) and a constant inverter means (52); said switched inverter means (51) for receiving said clock signal and said stop signal, and for providing a first voltage at said output terminal of said inverter means (51, 52) responsive to said clock signal when said stop signal is inactive; said constant inverter means (52) for receiving said clock signal and for providing a second voltage at said output terminal of said inverter means (51, 52) responsive to said clock signal and independent of said stop signal; a resistor (53) having a first terminal for receiving said clock signal, and a second terminal coupled to said output terminal of said inverter means (51, 52); logic means (54) coupled to said inverter means (51, 52), for providing a clock output signal in response to said output signal of said inverter means (51, 52), when said stop signal is inactive; and an internal circuit (43, 44) having a clock input terminal for receiving said clock output signal.
Claim 2
Dependent Claim
21 words
The integrated circuit (40) of claim 1, wherein said switched inverter means (51) comprises at least one switched inverter stage (60).
Claim 3
Dependent Claim
169 words
The integrated circuit (40) of claim 1 wherein said constant inverter means (52) comprises: a fifth transistor (101) having a first current electrode coupled to a first power supply voltage terminal, a control electrode coupled to a second power supply voltage terminal, and a second current electrode; a sixth transistor (102) having a first current electrode coupled to said second current electrode of said fifth transistor (101), a control electrode for receiving said clock signal, and a second current electrode coupled to said output terminal of said switched inverter means (51); a seventh transistor (103) having a first current electrode coupled to said second current electrode of said sixth transistor (102), a control electrode for receiving said clock signal, and a second current electrode; and an eighth transistor (104) having a first current electrode coupled to said second current electrode of said seventh transistor (103), a control electrode coupled to said first power supply voltage terminal, and a second current electrode coupled to said second power supply voltage terminal.
Claim 4
Dependent Claim
37 words
The integrated circuit (40) of claim 1 wherein said internal circuit (43, 44) comprises a central processing unit (28) having an input terminal for receiving said clock signal, and an output terminal for providing said stop signal.
Claim 5
Dependent Claim
156 words
An integrated circuit with a low-power mode (40), comprising: at least one switched inverter stage (60) each having an input terminal for receiving a clock signal, a control input terminal for receiving a stop signal, and an output terminal connected to an output node; an inverter (52) having an input terminal for receiving said clock signal, and an output terminal coupled to said output node; a resistor (53) having a first terminal coupled to said input terminals of each switched inverter stage (60) and to said input terminal of said inverter (52), and a second terminal coupled to said output node; and logic means (54) coupled to each switched inverter stage (60) and to said inverter (52), for providing a clock output signal in response to said a voltage on said output node, when said stop signal is inactive; and an internal circuit (43, 44) having a clock input terminal for receiving said clock output signal.
Claim 6
Dependent Claim
172 words
The integrated circuit (40) of claim 2 or claim 5, wherein each switched inverter stage (60) comprises: a first transistor (61) having a first current electrode coupled to a first power supply voltage terminal, a control electrode for receiving said stop signal, and a second current electrode; a second transistor (62) having a first current electrode coupled to said second current electrode of said first transistor (61), a control electrode for receiving said clock signal, and a second current electrode coupled to said output terminal of said at least one switched inverter stage (60); a third transistor (63) having a first current electrode coupled to said second current electrode of said second transistor (62), a control electrode for receiving said clock signal, and a second current electrode; and a fourth transistor (64) having a first current electrode coupled to said second current electrode of said third transistor (63), a control electrode for receiving a complement of said stop signal, and a second current electrode coupled to a second power supply voltage terminal.
Claim 7
Dependent Claim
165 words
The integrated circuit (40) of claim 5 wherein said inverter (52) comprises: a fifth transistor (101) having a first current electrode coupled to a first power supply voltage terminal, a control electrode coupled to a second power supply voltage terminal, and a second current electrode; a sixth transistor (102) having a first current electrode coupled to said second current electrode of said fifth transistor (101), a control electrode for receiving said clock signal, and a second current electrode coupled to said output terminal of said inverter (52); a seventh transistor (103) having a first current electrode coupled to said second current electrode of said sixth transistor (102), a control electrode for receiving said clock signal, and a second current electrode; and an eighth transistor (104) having a first current electrode coupled to said second current electrode of said seventh transistor (103), a control electrode coupled to said first power supply voltage terminal, and a second current electrode coupled to said second power supply voltage terminal.
Claim 8
Dependent Claim
60 words
The integrated circuit (40) of claim 1 or claim 5 wherein said logic means (54) comprises a NAND gate having a first input terminal coupled to said output terminal of said at least one switched inverter stage (60), a second input terminal for receiving a complement of said stop signal, and an output terminal for providing said clock output signal.
Claim 9
Dependent Claim
136 words
A clock amplifier circuit (41), comprising: at least one switched inverter stage (60) each having an input terminal for receiving a clock signal, a control input terminal for receiving a stop signal, and an output terminal connected to an output node; an inverter (52) having an input terminal for receiving said clock signal, and an output terminal coupled to said output node; a resistor (53) having a first terminal coupled to said input terminals of each switched inverter stage (60) and to said input terminal of said inverter (52), and a second terminal coupled to said output node; and logic means (54) coupled to each switched inverter stage (60) and to said inverter (52), for providing a clock output signal in response to said a voltage on said output node, when said stop signal is inactive.
Claim 10
Dependent Claim
169 words
The clock amplifier circuit (41) of claim 9, wherein each inverter stage (60) comprises: a first transistor (61) having a first current electrode coupled to a first power supply voltage terminal, a control electrode for receiving said stop signal, and a second current electrode; a second transistor (62) having a first current electrode coupled to said second current electrode of said first transistor (61), a control electrode for receiving said clock signal, and a second current electrode coupled to said output terminal of said at least one switched inverter stage (60); a third transistor (63) having a first current electrode coupled to said second current electrode of said second transistor (62), a control electrode for receiving said clock signal, and a second current electrode; and a fourth transistor (64) having a first current electrode coupled to said second current electrode of said third transistor (63), a control electrode for receiving a complement of said stop signal, and a second current electrode coupled to a second power supply voltage terminal.
References Cited (Backward Citations)
No citation records indexed.
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