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EP0622834A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Method to prevent latch-up and improve breakdown voltage in SOI MOSFETS

Assignee: BAE Systems Information and Electronic Systems Integration Inc
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Filing: 1994-02-17
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Granted: —
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Expires: 2014-02-17
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Abstract

Abstract SOI (silicon-on-insulator) technology has been touted as a promising approach for fabricating an advanced integrated circuits because of its advantage over bulk silicon circuits such as faster speed and improve radiation tolerance. One drawback to SOI is that parasitic bipolar induced latch-up/breakdown voltage levels severely limits the maximum supply voltage at which SOI circuits and devices can operate. When the parasitic device turns on, the SOI transistor cannot be switched off by changing the gate bias. What is described is a method whereby the operating voltage in which this effect occurs is significantly increased thus allowing circuit operation at reasonable power supply voltages. The method is to implant a neutral impurity ion such as krypton, xenon or germanium into the device (10) to form ion scattering centers. The size of the impurity atom must be much larger than the size of the silicon atom. The size difference generating a scattering center.

Inventors

  • 👤 Frederick T. Brady
  • 👤 Arthur Edenfeld
  • 👤 Nadim F. Haddad

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-03 02:17
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0321; H10D30/0323; H10D30/60; H10D30/67; H10D30/6704; H10D30/6708; H10P30/208; Y; Y10; Y10S; Y10S148/00; Y10S148/04

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 61 words
A method of fabricating integrated circuits having reduced parasitic latch-up and increase breakdown voltage comprising the steps of: a) providing a semiconductor substrate; b) growing an oxide layer on said substrate; c) blanket implanting the substrate with large diameter neutral atoms; d) forming active devices (10) on said substrate; and e) forming electrical conductors on said substrate to interconnect said devices.
Claim 2
Dependent Claim 24 words
The method of claim 1, wherein the order of the steps of the blanket implantation and the formation of active devices (10) is reversed.
Claim 3
Dependent Claim 12 words
The method of claim 1 or 2, wherein the substrate is silicon.
Claim 4
Dependent Claim 14 words
The method of claim 1 or 2, wherein the substrate is silicon-on-insulator (24, 14).
Claim 5
Independent Claim 16 words
The method of one of claims 1 to 4, wherein said integrated circuits are MOSFETs (10).
Claim 6
Independent Claim 26 words
The method of one of claims 1 to 5, wherein said large diameter neutral atoms are selected from the group consisting of krypton, argon, and germanium.
Claim 7
Independent Claim 34 words
The method of one of claims 1 to 6, wherein said large diameter neutral atom is germanium implanted at 50 to 60 KeV with a dose in the range of 1E14 to 1E16 cm-2.
Claim 8
Dependent Claim 37 words
In an integrated circuit including a substrate, semiconductor devices formed on said substrate, and electrical conductors interconnecting said semiconductor devices, the improvement comprising the addition of a blanket implant of large diameter neutral atoms into said substrate.
Claim 9
Dependent Claim 22 words
The method as claimed in claim 8, wherein said neutral atom is selected from the group consisting of krypton, argon, and germanium.

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